Lines Matching refs:smu
157 static int smu_v14_0_0_init_smc_tables(struct smu_context *smu)
159 struct smu_table_context *smu_table = &smu->smu_table;
199 static int smu_v14_0_0_fini_smc_tables(struct smu_context *smu)
201 struct smu_table_context *smu_table = &smu->smu_table;
218 static int smu_v14_0_0_system_features_control(struct smu_context *smu, bool en)
220 struct amdgpu_device *adev = smu->adev;
224 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
229 static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
233 struct smu_table_context *smu_table = &smu->smu_table;
238 ret = smu_cmn_get_metrics_table(smu, NULL, false);
271 if ((smu->smc_fw_version > 0x5d4600))
349 static int smu_v14_0_0_read_sensor(struct smu_context *smu,
360 ret = smu_v14_0_0_get_smu_metrics_data(smu,
366 ret = smu_v14_0_0_get_smu_metrics_data(smu,
372 ret = smu_v14_0_0_get_smu_metrics_data(smu,
378 ret = smu_v14_0_0_get_smu_metrics_data(smu,
384 ret = smu_v14_0_0_get_smu_metrics_data(smu,
390 ret = smu_v14_0_0_get_smu_metrics_data(smu,
396 ret = smu_v14_0_0_get_smu_metrics_data(smu,
403 ret = smu_v14_0_0_get_smu_metrics_data(smu,
410 ret = smu_v14_0_0_get_smu_metrics_data(smu,
416 ret = smu_v14_0_0_get_smu_metrics_data(smu,
422 ret = smu_v14_0_0_get_smu_metrics_data(smu,
428 ret = smu_v14_0_0_get_smu_metrics_data(smu,
441 static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
446 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
454 static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,
459 Watermarks_t *table = smu->smu_table.watermarks_table;
496 smu->watermarks_bitmap |= WATERMARKS_EXIST;
498 /* pass data to smu controller */
499 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
500 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
501 ret = smu_cmn_write_watermarks_table(smu);
503 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
506 smu->watermarks_bitmap |= WATERMARKS_LOADED;
512 static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
515 struct smu_table_context *smu_table = &smu->smu_table;
521 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
589 static int smu_v14_0_0_mode2_reset(struct smu_context *smu)
593 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
597 dev_err(smu->adev->dev, "Failed to mode2 reset!\n");
602 static int smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu,
607 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
656 static int smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu,
661 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
700 static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
705 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
706 smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
707 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
708 smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
713 static bool smu_v14_0_0_clk_dpm_is_enabled(struct smu_context *smu,
741 return smu_cmn_feature_is_enabled(smu, feature_id);
744 static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
749 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
754 if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
758 clock_limit = smu->smu_table.boot_values.uclk;
761 clock_limit = smu->smu_table.boot_values.fclk;
765 clock_limit = smu->smu_table.boot_values.gfxclk;
768 clock_limit = smu->smu_table.boot_values.socclk;
772 clock_limit = smu->smu_table.boot_values.vclk;
776 clock_limit = smu->smu_table.boot_values.dclk;
820 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
854 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
864 static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
869 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
874 if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type)) {
878 clock_limit = smu->smu_table.boot_values.uclk;
881 clock_limit = smu->smu_table.boot_values.fclk;
885 clock_limit = smu->smu_table.boot_values.gfxclk;
888 clock_limit = smu->smu_table.boot_values.socclk;
891 clock_limit = smu->smu_table.boot_values.vclk;
894 clock_limit = smu->smu_table.boot_values.dclk;
934 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
966 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
976 static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
981 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
982 smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
983 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
984 smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
989 static int smu_v14_0_0_get_current_clk_freq(struct smu_context *smu,
1019 return smu_v14_0_0_get_smu_metrics_data(smu, member_type, value);
1022 static int smu_v14_0_1_get_dpm_level_count(struct smu_context *smu,
1026 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1053 static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu,
1057 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1082 static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
1086 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1087 smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
1088 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1089 smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
1094 static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
1107 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1109 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1114 smu->gfx_default_hard_min_freq,
1115 smu->gfx_default_soft_max_freq);
1124 ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
1128 ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count);
1133 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, i, &value);
1143 ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value);
1146 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1147 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1169 static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu,
1177 if (!smu_v14_0_0_clk_dpm_is_enabled(smu, clk_type))
1208 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
1212 return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
1216 static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
1232 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1236 ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1240 ret = smu_v14_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1250 static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
1253 struct amdgpu_device *adev = smu->adev;
1261 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1262 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1263 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1269 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1270 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1271 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1277 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1278 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1279 smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1296 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1303 smu->gfx_actual_hard_min_freq = sclk_min;
1304 smu->gfx_actual_soft_max_freq = sclk_max;
1308 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1317 ret = smu_v14_0_0_set_soft_freq_limited_range(smu,
1328 static int smu_v14_0_1_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1330 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1332 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1333 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1334 smu->gfx_actual_hard_min_freq = 0;
1335 smu->gfx_actual_soft_max_freq = 0;
1340 static int smu_v14_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1342 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1344 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1345 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1346 smu->gfx_actual_hard_min_freq = 0;
1347 smu->gfx_actual_soft_max_freq = 0;
1352 static int smu_v14_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1354 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1355 smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);
1356 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1357 smu_v14_0_1_set_fine_grain_gfx_freq_parameters(smu);
1362 static int smu_v14_0_0_set_vpe_enable(struct smu_context *smu,
1365 return smu_cmn_send_smc_msg_with_param(smu, enable ?
1370 static int smu_v14_0_0_set_umsch_mm_enable(struct smu_context *smu,
1373 return smu_cmn_send_smc_msg_with_param(smu, enable ?
1378 static int smu_14_0_1_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1380 DpmClocks_t_v14_0_1 *clk_table = smu->smu_table.clocks_table;
1397 static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1399 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1416 static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1418 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1419 smu_14_0_0_get_dpm_table(smu, clock_table);
1420 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1421 smu_14_0_1_get_dpm_table(smu, clock_table);
1459 static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)
1461 struct amdgpu_device *adev = smu->adev;
1463 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1464 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1465 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1468 void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu)
1471 smu->ppt_funcs = &smu_v14_0_0_ppt_funcs;
1472 smu->message_map = smu_v14_0_0_message_map;
1473 smu->feature_map = smu_v14_0_0_feature_mask_map;
1474 smu->table_map = smu_v14_0_0_table_map;
1475 smu->is_apu = true;
1477 smu_v14_0_0_set_smu_mailbox_registers(smu);