Lines Matching refs:smu
58 int smu_v14_0_init_microcode(struct smu_context *smu)
60 struct amdgpu_device *adev = smu->adev;
68 /* doesn't need to load smu firmware in IOV mode */
99 void smu_v14_0_fini_microcode(struct smu_context *smu)
101 struct amdgpu_device *adev = smu->adev;
107 int smu_v14_0_load_microcode(struct smu_context *smu)
110 struct amdgpu_device *adev = smu->adev;
150 int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
152 struct amdgpu_device *adev = smu->adev;
158 /* doesn't need to load smu firmware in IOV mode */
173 pptable_id = smu->smu_table.boot_values.pp_table_id;
180 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
184 smu->pptable_firmware.data = table;
185 smu->pptable_firmware.size = size;
189 ucode->fw = &smu->pptable_firmware;
191 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
196 int smu_v14_0_check_fw_status(struct smu_context *smu)
198 struct amdgpu_device *adev = smu->adev;
211 int smu_v14_0_check_fw_version(struct smu_context *smu)
213 struct amdgpu_device *adev = smu->adev;
218 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
226 if (smu->is_apu)
231 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
234 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
237 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
241 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
243 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
248 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
259 if (if_version != smu->smc_driver_if_version) {
260 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
261 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
262 smu->smc_driver_if_version, if_version,
270 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
272 struct amdgpu_device *adev = smu->adev;
285 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
288 struct amdgpu_device *adev = smu->adev;
312 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
314 struct amdgpu_device *adev = smu->adev;
334 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
340 struct amdgpu_device *adev = smu->adev;
353 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
360 ret = smu_v14_0_set_pptable_v2_0(smu, table, size);
363 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id);
373 int smu_v14_0_setup_pptable(struct smu_context *smu)
375 struct amdgpu_device *adev = smu->adev;
385 pptable_id = smu->smu_table.boot_values.pp_table_id;
390 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size);
392 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
397 if (!smu->smu_table.power_play_table)
398 smu->smu_table.power_play_table = table;
399 if (!smu->smu_table.power_play_table_size)
400 smu->smu_table.power_play_table_size = size;
405 int smu_v14_0_init_smc_tables(struct smu_context *smu)
407 struct smu_table_context *smu_table = &smu->smu_table;
462 int smu_v14_0_fini_smc_tables(struct smu_context *smu)
464 struct smu_table_context *smu_table = &smu->smu_table;
465 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
503 int smu_v14_0_init_power(struct smu_context *smu)
505 struct smu_power_context *smu_power = &smu->smu_power;
519 int smu_v14_0_fini_power(struct smu_context *smu)
521 struct smu_power_context *smu_power = &smu->smu_power;
533 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
548 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
554 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n");
563 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
564 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
565 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
566 smu->smu_table.boot_values.socclk = 0;
567 smu->smu_table.boot_values.dcefclk = 0;
568 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
569 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
570 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
571 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
572 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
573 smu->smu_table.boot_values.pp_table_id = 0;
577 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
578 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
579 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
580 smu->smu_table.boot_values.socclk = 0;
581 smu->smu_table.boot_values.dcefclk = 0;
582 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
583 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
584 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
585 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
586 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
587 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
592 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
593 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
594 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
595 smu->smu_table.boot_values.socclk = 0;
596 smu->smu_table.boot_values.dcefclk = 0;
597 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
598 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
599 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
600 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
601 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
602 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
606 smu->smu_table.boot_values.format_revision = header->format_revision;
607 smu->smu_table.boot_values.content_revision = header->content_revision;
611 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
617 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
618 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
619 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
620 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
626 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
627 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
628 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
629 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
630 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
632 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
641 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
643 struct smu_table_context *smu_table = &smu->smu_table;
656 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
664 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
672 int smu_v14_0_set_driver_table_location(struct smu_context *smu)
674 struct smu_table *driver_table = &smu->smu_table.driver_table;
678 ret = smu_cmn_send_smc_msg_with_param(smu,
683 ret = smu_cmn_send_smc_msg_with_param(smu,
692 int smu_v14_0_set_tool_table_location(struct smu_context *smu)
695 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
698 ret = smu_cmn_send_smc_msg_with_param(smu,
703 ret = smu_cmn_send_smc_msg_with_param(smu,
712 int smu_v14_0_set_allowed_mask(struct smu_context *smu)
714 struct smu_feature *feature = &smu->smu_feature;
724 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
729 return smu_cmn_send_smc_msg_with_param(smu,
735 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
738 struct amdgpu_device *adev = smu->adev;
747 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
749 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
758 int smu_v14_0_system_features_control(struct smu_context *smu,
761 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
765 int smu_v14_0_notify_display_change(struct smu_context *smu)
769 if (!smu->pm_enabled)
772 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
773 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
774 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
779 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
785 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
788 power_src = smu_cmn_to_asic_specific_index(smu,
790 smu->adev->pm.ac_power ?
796 ret = smu_cmn_send_smc_msg_with_param(smu,
801 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
806 int smu_v14_0_set_power_limit(struct smu_context *smu,
815 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
816 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
820 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
822 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
826 smu->current_power_limit = limit;
885 int smu_v14_0_register_irq_handler(struct smu_context *smu)
887 struct amdgpu_device *adev = smu->adev;
888 struct amdgpu_irq_src *irq_src = &smu->irq_source;
908 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
913 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
914 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
919 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
926 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg);
935 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
942 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
946 clock_limit = smu->smu_table.boot_values.uclk;
950 clock_limit = smu->smu_table.boot_values.gfxclk;
953 clock_limit = smu->smu_table.boot_values.socclk;
969 clk_id = smu_cmn_to_asic_specific_index(smu,
979 if (smu->adev->pm.ac_power)
980 ret = smu_cmn_send_smc_msg_with_param(smu,
985 ret = smu_cmn_send_smc_msg_with_param(smu,
994 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1003 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
1011 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1014 clk_id = smu_cmn_to_asic_specific_index(smu,
1022 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1030 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1040 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
1051 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1054 clk_id = smu_cmn_to_asic_specific_index(smu,
1062 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1070 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1079 int smu_v14_0_set_performance_level(struct smu_context *smu,
1083 smu->smu_dpm.dpm_context;
1097 &smu->pstate_table;
1098 struct amdgpu_device *adev = smu->adev;
1169 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1181 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1193 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1208 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1223 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1235 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1249 int smu_v14_0_set_power_source(struct smu_context *smu,
1254 pwr_source = smu_cmn_to_asic_specific_index(smu,
1260 return smu_cmn_send_smc_msg_with_param(smu,
1266 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
1277 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1280 clk_id = smu_cmn_to_asic_specific_index(smu,
1288 ret = smu_cmn_send_smc_msg_with_param(smu,
1300 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
1306 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1311 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
1322 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1325 clk_id = smu_cmn_to_asic_specific_index(smu,
1333 ret = smu_cmn_send_smc_msg_with_param(smu,
1349 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
1357 ret = smu_v14_0_get_dpm_level_count(smu,
1361 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1365 ret = smu_v14_0_get_fine_grained_status(smu,
1369 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1374 ret = smu_v14_0_get_dpm_freq_by_index(smu,
1379 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1395 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
1398 struct amdgpu_device *adev = smu->adev;
1408 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1412 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1416 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1428 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
1431 struct amdgpu_device *adev = smu->adev;
1441 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1445 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1449 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1461 int smu_v14_0_run_btc(struct smu_context *smu)
1465 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1467 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1472 int smu_v14_0_gpo_control(struct smu_context *smu,
1477 res = smu_cmn_send_smc_msg_with_param(smu,
1482 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1487 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
1490 struct amdgpu_device *adev = smu->adev;
1493 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1494 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1501 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1502 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1509 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1510 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1517 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1518 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1525 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1526 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1533 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1534 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1541 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1542 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1549 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1550 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1560 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
1565 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1566 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1571 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
1574 struct smu_baco_context *smu_baco = &smu->smu_baco;
1577 ret = smu_cmn_send_smc_msg_with_param(smu,
1593 bool smu_v14_0_baco_is_support(struct smu_context *smu)
1595 struct smu_baco_context *smu_baco = &smu->smu_baco;
1597 if (amdgpu_sriov_vf(smu->adev) ||
1602 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1605 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1606 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1612 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
1614 struct smu_baco_context *smu_baco = &smu->smu_baco;
1619 int smu_v14_0_baco_set_state(struct smu_context *smu,
1622 struct smu_baco_context *smu_baco = &smu->smu_baco;
1623 struct amdgpu_device *adev = smu->adev;
1626 if (smu_v14_0_baco_get_state(smu) == state)
1630 ret = smu_cmn_send_smc_msg_with_param(smu,
1636 ret = smu_cmn_send_smc_msg(smu,
1653 int smu_v14_0_baco_enter(struct smu_context *smu)
1657 ret = smu_v14_0_baco_set_state(smu,
1667 int smu_v14_0_baco_exit(struct smu_context *smu)
1669 return smu_v14_0_baco_set_state(smu,
1673 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1676 struct amdgpu_device *adev = smu->adev;
1679 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
1683 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1685 return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE);
1688 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
1690 struct smu_table_context *smu_table = &smu->smu_table;
1692 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1696 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
1700 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1710 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1715 if (input[1] < smu->gfx_default_hard_min_freq) {
1716 dev_warn(smu->adev->dev,
1718 input[1], smu->gfx_default_hard_min_freq);
1721 smu->gfx_actual_hard_min_freq = input[1];
1723 if (input[1] > smu->gfx_default_soft_max_freq) {
1724 dev_warn(smu->adev->dev,
1726 input[1], smu->gfx_default_soft_max_freq);
1729 smu->gfx_actual_soft_max_freq = input[1];
1736 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1739 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1740 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1744 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1747 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1748 dev_err(smu->adev->dev,
1750 smu->gfx_actual_hard_min_freq,
1751 smu->gfx_actual_soft_max_freq);
1755 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1756 smu->gfx_actual_hard_min_freq,
1759 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1764 smu->gfx_actual_soft_max_freq,
1767 dev_err(smu->adev->dev, "Set soft max sclk failed!");