Lines Matching refs:min
936 uint32_t *min, uint32_t *max)
961 if (min)
962 *min = clock_limit / 100;
993 if (min) {
994 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1005 uint32_t min,
1028 if (min > 0) {
1029 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1042 uint32_t min,
1048 if (min <= 0 && max <= 0)
1068 if (min > 0) {
1069 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1117 sclk_min = sclk_max = gfx_table->min;
1118 mclk_min = mclk_max = mem_table->min;
1119 socclk_min = socclk_max = soc_table->min;
1120 vclk_min = vclk_max = vclk_table->min;
1121 dclk_min = dclk_max = dclk_table->min;
1122 fclk_min = fclk_max = fclk_table->min;
1125 sclk_min = gfx_table->min;
1127 mclk_min = mem_table->min;
1129 socclk_min = soc_table->min;
1131 vclk_min = vclk_table->min;
1133 dclk_min = dclk_table->min;
1135 fclk_min = fclk_table->min;
1147 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1150 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1176 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1188 pstate_table->uclk_pstate.curr.min = mclk_min;
1200 pstate_table->socclk_pstate.curr.min = socclk_min;
1215 pstate_table->vclk_pstate.curr.min = vclk_min;
1230 pstate_table->dclk_pstate.curr.min = dclk_min;
1242 pstate_table->fclk_pstate.curr.min = fclk_min;
1387 single_dpm_table->min = clk;
1759 dev_err(smu->adev->dev, "Set hard min sclk failed!");