Lines Matching refs:smu
266 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
269 struct amdgpu_device *adev = smu->adev;
335 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
337 struct smu_table_context *table_context = &smu->smu_table;
340 struct smu_baco_context *smu_baco = &smu->smu_baco;
349 smu->dc_controlled_by_gpio = true;
361 smu->od_enabled = false;
368 * smu->od_settings just points to the actual overdrive_table
370 smu->od_settings = &powerplay_table->overdrive_table;
375 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
377 struct smu_table_context *table_context = &smu->smu_table;
380 struct amdgpu_device *adev = smu->adev;
391 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
393 struct amdgpu_device *adev = smu->adev;
413 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
415 struct smu_table_context *table_context = &smu->smu_table;
428 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
438 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
442 struct smu_table_context *smu_table = &smu->smu_table;
446 ret = smu_cmn_get_combo_pptable(smu);
456 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
458 struct smu_table_context *smu_table = &smu->smu_table;
459 struct amdgpu_device *adev = smu->adev;
467 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
473 ret = smu_v13_0_7_store_powerplay_table(smu);
482 ret = smu_v13_0_7_append_powerplay_table(smu);
487 ret = smu_v13_0_7_check_powerplay_table(smu);
494 static int smu_v13_0_7_tables_init(struct smu_context *smu)
496 struct smu_table_context *smu_table = &smu->smu_table;
545 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
547 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
559 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
563 ret = smu_v13_0_7_tables_init(smu);
567 ret = smu_v13_0_7_allocate_dpm_context(smu);
571 return smu_v13_0_init_smc_tables(smu);
574 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
576 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
577 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
586 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
587 ret = smu_v13_0_set_single_dpm_table(smu,
594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
602 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
603 ret = smu_v13_0_set_single_dpm_table(smu,
618 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
626 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
627 ret = smu_v13_0_set_single_dpm_table(smu,
634 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
642 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
643 ret = smu_v13_0_set_single_dpm_table(smu,
650 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
658 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
659 ret = smu_v13_0_set_single_dpm_table(smu,
666 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
674 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
675 ret = smu_v13_0_set_single_dpm_table(smu,
682 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
708 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
709 ret = smu_v13_0_set_single_dpm_table(smu,
716 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
725 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
730 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
737 static void smu_v13_0_7_dump_pptable(struct smu_context *smu)
739 struct smu_table_context *table_context = &smu->smu_table;
743 dev_info(smu->adev->dev, "Dumped PPTable:\n");
745 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
746 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
747 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
763 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
767 struct smu_table_context *smu_table = &smu->smu_table;
772 ret = smu_cmn_get_metrics_table(smu,
888 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
894 smu->smu_dpm.dpm_context;
927 dev_err(smu->adev->dev, "Unsupported clock type!\n");
939 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
944 struct smu_table_context *table_context = &smu->smu_table;
954 ret = smu_v13_0_7_get_smu_metrics_data(smu,
960 ret = smu_v13_0_7_get_smu_metrics_data(smu,
966 ret = smu_v13_0_7_get_smu_metrics_data(smu,
972 ret = smu_v13_0_7_get_smu_metrics_data(smu,
978 ret = smu_v13_0_7_get_smu_metrics_data(smu,
984 ret = smu_v13_0_7_get_smu_metrics_data(smu,
990 ret = smu_v13_0_7_get_smu_metrics_data(smu,
997 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1004 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1018 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
1025 clk_id = smu_cmn_to_asic_specific_index(smu,
1063 return smu_v13_0_7_get_smu_metrics_data(smu,
1068 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
1071 PPTable_t *pptable = smu->smu_table.driver_pptable;
1078 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
1083 PPTable_t *pptable = smu->smu_table.driver_pptable;
1146 static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
1149 struct amdgpu_device *adev = smu->adev;
1157 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
1162 ret = smu_cmn_update_table(smu,
1168 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1173 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
1178 ret = smu_cmn_update_table(smu,
1184 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1189 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
1193 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1196 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1249 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1251 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1291 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1297 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1323 if (!smu_v13_0_7_is_od_feature_supported(smu,
1334 if (!smu_v13_0_7_is_od_feature_supported(smu,
1345 if (!smu_v13_0_7_is_od_feature_supported(smu,
1355 if (!smu_v13_0_7_is_od_feature_supported(smu,
1367 smu_v13_0_7_get_od_setting_limits(smu,
1374 smu_v13_0_7_get_od_setting_limits(smu,
1384 if (!smu_v13_0_7_is_od_feature_supported(smu,
1393 smu_v13_0_7_get_od_setting_limits(smu,
1402 if (!smu_v13_0_7_is_od_feature_supported(smu,
1411 smu_v13_0_7_get_od_setting_limits(smu,
1420 if (!smu_v13_0_7_is_od_feature_supported(smu,
1429 smu_v13_0_7_get_od_setting_limits(smu,
1438 if (!smu_v13_0_7_is_od_feature_supported(smu,
1447 smu_v13_0_7_get_od_setting_limits(smu,
1456 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1457 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1458 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1463 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1464 smu_v13_0_7_get_od_setting_limits(smu,
1468 smu_v13_0_7_get_od_setting_limits(smu,
1476 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1477 smu_v13_0_7_get_od_setting_limits(smu,
1481 smu_v13_0_7_get_od_setting_limits(smu,
1489 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1490 smu_v13_0_7_get_od_setting_limits(smu,
1506 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)
1508 struct smu_table_context *table_context = &smu->smu_table;
1513 struct amdgpu_device *adev = smu->adev;
1559 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
1564 struct smu_table_context *table_context = &smu->smu_table;
1567 struct amdgpu_device *adev = smu->adev;
1575 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1588 smu_v13_0_7_get_od_setting_limits(smu,
1604 smu_v13_0_7_get_od_setting_limits(smu,
1636 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1649 smu_v13_0_7_get_od_setting_limits(smu,
1665 smu_v13_0_7_get_od_setting_limits(smu,
1697 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1702 smu_v13_0_7_get_od_setting_limits(smu,
1719 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1728 smu_v13_0_7_get_od_setting_limits(smu,
1739 smu_v13_0_7_get_od_setting_limits(smu,
1757 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1762 smu_v13_0_7_get_od_setting_limits(smu,
1779 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1784 smu_v13_0_7_get_od_setting_limits(smu,
1801 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1806 smu_v13_0_7_get_od_setting_limits(smu,
1823 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1828 smu_v13_0_7_get_od_setting_limits(smu,
1846 ret = smu_v13_0_7_od_restore_table_single(smu, input[0]);
1870 smu_v13_0_7_dump_od_table(smu, od_table);
1872 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
1886 smu->user_dpm_profile.user_od = false;
1888 smu->user_dpm_profile.user_od = true;
1899 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1903 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1964 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1983 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
1986 struct smu_table_context *table_context = &smu->smu_table;
1989 PPTable_t *pptable = smu->smu_table.driver_pptable;
2014 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
2017 struct smu_table_context *smu_table = &smu->smu_table;
2024 ret = smu_cmn_get_metrics_table(smu,
2094 static void smu_v13_0_7_set_supported_od_feature_mask(struct smu_context *smu)
2096 struct amdgpu_device *adev = smu->adev;
2098 if (smu_v13_0_7_is_od_feature_supported(smu,
2112 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
2115 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2117 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2119 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2124 ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table);
2128 smu_v13_0_7_dump_od_table(smu, boot_od_table);
2138 if (!smu->adev->in_suspend) {
2142 smu->user_dpm_profile.user_od = false;
2143 } else if (smu->user_dpm_profile.user_od) {
2177 smu_v13_0_7_set_supported_od_feature_mask(smu);
2182 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu)
2184 struct smu_table_context *table_context = &smu->smu_table;
2193 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table);
2201 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
2204 smu->smu_dpm.dpm_context;
2218 &smu->pstate_table;
2219 struct smu_table_context *table_context = &smu->smu_table;
2260 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
2268 ret = smu_v13_0_7_get_smu_metrics_data(smu,
2272 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2282 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
2288 return smu_v13_0_7_get_smu_metrics_data(smu,
2293 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
2295 struct smu_table_context *table_context = &smu->smu_table;
2306 return smu_cmn_send_smc_msg_with_param(smu,
2312 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
2318 struct smu_table_context *table_context = &smu->smu_table;
2326 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2327 power_limit = smu->adev->pm.ac_power ?
2337 if (smu->od_enabled &&
2338 (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT))) {
2341 } else if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2347 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2363 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
2382 (i == smu->power_profile_mode) ? "* " : " ");
2388 workload_type = smu_cmn_to_asic_specific_index(smu,
2398 result = smu_cmn_update_table(smu,
2402 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2437 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
2445 smu->power_profile_mode = input[size];
2447 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) {
2448 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2452 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2454 ret = smu_cmn_update_table(smu,
2458 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2483 ret = smu_cmn_update_table(smu,
2487 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2493 workload_type = smu_cmn_to_asic_specific_index(smu,
2495 smu->power_profile_mode);
2498 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2504 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
2511 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2521 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
2523 struct amdgpu_device *adev = smu->adev;
2532 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
2535 return smu_cmn_send_smc_msg_with_param(smu,
2541 static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
2543 return smu->smc_fw_version > 0x00524600;
2546 static int smu_v13_0_7_set_power_limit(struct smu_context *smu,
2550 PPTable_t *pptable = smu->smu_table.driver_pptable;
2553 struct smu_table_context *table_context = &smu->smu_table;
2562 if (smu->current_power_limit > msg_limit) {
2566 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2568 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2572 return smu_v13_0_set_power_limit(smu, limit_type, limit);
2573 } else if (smu->od_enabled) {
2574 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
2581 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2583 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2587 smu->current_power_limit = limit;
2666 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
2668 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
2669 smu->message_map = smu_v13_0_7_message_map;
2670 smu->clock_map = smu_v13_0_7_clk_map;
2671 smu->feature_map = smu_v13_0_7_feature_mask_map;
2672 smu->table_map = smu_v13_0_7_table_map;
2673 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
2674 smu->workload_map = smu_v13_0_7_workload_map;
2675 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
2676 smu_v13_0_set_smu_mailbox_registers(smu);