swsmu/smu13/smu_v13_0_6_ppt.c

1466 	uint32_t val = 0;
1471 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1472 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1473 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1478 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1479 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1480 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1481 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1483 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1484 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1485 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
2567 				       int idx, int offset, uint32_t *val)
2584 	return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
2588 				     int idx, int offset, uint32_t *val, int count)
2592 	if (!val)
2596 		ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
2635 			     int idx, int reg_idx, uint64_t *val)
2641 	if (!val || reg_idx >= MCA_REG_IDX_COUNT)
2648 	*val = (uint64_t)data[1] << 32 | data[0];
2650 	dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
2651 		type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
2676 static int mca_decode_ipid_to_hwip(uint64_t val)
2682 	hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
2683 	mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3077 				       int idx, int offset, u32 *val)
3094 	return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3098 				     int idx, int offset, u32 *val, int count)
3102 	if (!val)
3106 		ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3115 			     int idx, int reg_idx, u64 *val)
3121 	if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3128 	*val = (u64)data[1] << 32 | data[0];
3130 	dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3131 		type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);