swsmu/smu13/smu_v13_0_6_ppt.c

116 			     enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
118 			      enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
1408 				   struct amdgpu_iv_entry *entry)
1413 	uint32_t client_id = entry->client_id;
1414 	uint32_t ctxid = entry->src_data[0];
1415 	uint32_t src_id = entry->src_id;
1446 							entry->src_data[1]);
2611 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
2613 	u64 ipid = entry->regs[MCA_REG_IDX_IPID];
2657 			     int idx, struct mca_bank_entry *entry)
2662 	for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
2663 		ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
2668 	entry->idx = idx;
2669 	entry->type = type;
2671 	mca_bank_entry_info_decode(entry, &entry->info);
2699 				     enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2705 	status0 = entry->regs[MCA_REG_IDX_STATUS];
2707 	odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2720 			entry->regs[MCA_REG_IDX_STATUS],
2721 			entry->regs[MCA_REG_IDX_IPID],
2722 			entry->regs[MCA_REG_IDX_ADDR]);
2728 					  enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
2734 	ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
2735 	err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
2763 				     enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2767 	status0 = entry->regs[MCA_REG_IDX_STATUS];
2779 		misc0 = entry->regs[MCA_REG_IDX_MISC0];
2787 				     enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
2791 	status0 = entry->regs[MCA_REG_IDX_STATUS];
2805 	misc0 = entry->regs[MCA_REG_IDX_MISC0];
2812 				      enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2816 	instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2831 				  enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2836 	instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
2842 		errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
2845 		errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
2920 			      enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
2922 	if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
2926 		return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
2934 	struct mca_bank_entry entry;
2947 		memset(&entry, 0, sizeof(entry));
2948 		ret = mca_get_mca_entry(adev, type, i, &entry);
2952 		if (mca_ras && !mca_bank_is_valid(adev, mca_ras, type, &entry))
2955 		ret = amdgpu_mca_bank_set_add_entry(mca_set, &entry);
2981 					 struct mca_bank_entry *entry, uint32_t *count)
2985 	if (!entry || !count)
2992 	if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
2997 	return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3001 				 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3003 	return mca_get_mca_entry(adev, type, idx, entry);