Lines Matching defs:smu
124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
126 struct smu_table_context *smu_table = &smu->smu_table;
166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
168 struct smu_table_context *smu_table = &smu->smu_table;
185 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
187 struct amdgpu_device *adev = smu->adev;
191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
196 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
202 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
205 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
211 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
216 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
219 ret = smu_cmn_send_smc_msg_with_param(smu,
227 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
232 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
240 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
246 dev_err(smu->adev->dev, "Failed to mode reset!\n");
251 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
253 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
256 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
260 struct smu_table_context *smu_table = &smu->smu_table;
265 ret = smu_cmn_get_metrics_table(smu, NULL, false);
319 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
330 ret = smu_v13_0_5_get_smu_metrics_data(smu,
336 ret = smu_v13_0_5_get_smu_metrics_data(smu,
342 ret = smu_v13_0_5_get_smu_metrics_data(smu,
348 ret = smu_v13_0_5_get_smu_metrics_data(smu,
354 ret = smu_v13_0_5_get_smu_metrics_data(smu,
361 ret = smu_v13_0_5_get_smu_metrics_data(smu,
368 ret = smu_v13_0_5_get_smu_metrics_data(smu,
374 ret = smu_v13_0_5_get_smu_metrics_data(smu,
380 ret = smu_v13_0_5_get_smu_metrics_data(smu,
386 ret = smu_v13_0_5_get_smu_metrics_data(smu,
400 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
405 Watermarks_t *table = smu->smu_table.watermarks_table;
443 smu->watermarks_bitmap |= WATERMARKS_EXIST;
446 /* pass data to smu controller */
447 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
448 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
449 ret = smu_cmn_write_watermarks_table(smu);
451 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
454 smu->watermarks_bitmap |= WATERMARKS_LOADED;
460 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
463 struct smu_table_context *smu_table = &smu->smu_table;
469 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
498 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
500 struct smu_table_context *smu_table = &smu->smu_table;
502 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
505 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
508 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
518 dev_err(smu->adev->dev, "Input parameter number not correct\n");
523 if (input[1] < smu->gfx_default_hard_min_freq) {
524 dev_warn(smu->adev->dev,
526 input[1], smu->gfx_default_hard_min_freq);
529 smu->gfx_actual_hard_min_freq = input[1];
531 if (input[1] > smu->gfx_default_soft_max_freq) {
532 dev_warn(smu->adev->dev,
534 input[1], smu->gfx_default_soft_max_freq);
537 smu->gfx_actual_soft_max_freq = input[1];
544 dev_err(smu->adev->dev, "Input parameter number not correct\n");
547 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
548 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
553 dev_err(smu->adev->dev, "Input parameter number not correct\n");
556 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
557 dev_err(smu->adev->dev,
559 smu->gfx_actual_hard_min_freq,
560 smu->gfx_actual_soft_max_freq);
564 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
565 smu->gfx_actual_hard_min_freq, NULL);
567 dev_err(smu->adev->dev, "Set hard min sclk failed!");
571 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
572 smu->gfx_actual_soft_max_freq, NULL);
574 dev_err(smu->adev->dev, "Set soft max sclk failed!");
586 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
607 return smu_cmn_send_smc_msg_with_param(smu,
614 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
617 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
621 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
646 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
651 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
690 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
716 return smu_cmn_feature_is_enabled(smu, feature_id);
719 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
724 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
729 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
733 clock_limit = smu->smu_table.boot_values.uclk;
736 clock_limit = smu->smu_table.boot_values.fclk;
740 clock_limit = smu->smu_table.boot_values.gfxclk;
743 clock_limit = smu->smu_table.boot_values.socclk;
746 clock_limit = smu->smu_table.boot_values.vclk;
749 clock_limit = smu->smu_table.boot_values.dclk;
789 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
819 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
829 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
839 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
862 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
866 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
874 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
887 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
889 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
894 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
900 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
904 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
910 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value);
920 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
923 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
924 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
948 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
961 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
965 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
969 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
982 static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
996 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
998 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
1001 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1004 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1014 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
1017 struct amdgpu_device *adev = smu->adev;
1025 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1026 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1027 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1033 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1034 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1035 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1041 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1042 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1043 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1048 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1049 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1050 smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1064 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1071 smu->gfx_actual_hard_min_freq = sclk_min;
1072 smu->gfx_actual_soft_max_freq = sclk_max;
1076 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1085 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1095 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1097 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1099 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1100 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1101 smu->gfx_actual_hard_min_freq = 0;
1102 smu->gfx_actual_soft_max_freq = 0;
1136 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1138 struct amdgpu_device *adev = smu->adev;
1140 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1141 smu->message_map = smu_v13_0_5_message_map;
1142 smu->feature_map = smu_v13_0_5_feature_mask_map;
1143 smu->table_map = smu_v13_0_5_table_map;
1144 smu->is_apu = true;
1145 smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION;
1146 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1147 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1148 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);