Lines Matching refs:smu
58 int smu_v12_0_check_fw_status(struct smu_context *smu)
60 struct amdgpu_device *adev = smu->adev;
73 int smu_v12_0_check_fw_version(struct smu_context *smu)
75 struct amdgpu_device *adev = smu->adev;
80 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
88 if (smu->is_apu)
99 if (if_version != smu->smc_driver_if_version) {
100 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
101 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
102 smu->smc_driver_if_version, if_version,
104 dev_info(smu->adev->dev, "SMU driver if version not matched\n");
110 int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
112 if (!smu->is_apu)
116 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownSdma, NULL);
118 return smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpSdma, NULL);
121 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
124 if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) || smu->adev->in_s0ix)
127 return smu_cmn_send_smc_msg_with_param(smu,
136 * @smu: amdgpu_device pointer
145 uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
149 struct amdgpu_device *adev = smu->adev;
158 int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
163 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
166 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
169 while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
182 int smu_v12_0_fini_smc_tables(struct smu_context *smu)
184 struct smu_table_context *smu_table = &smu->smu_table;
201 int smu_v12_0_set_default_dpm_tables(struct smu_context *smu)
203 struct smu_table_context *smu_table = &smu->smu_table;
205 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
208 int smu_v12_0_mode2_reset(struct smu_context *smu)
210 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
213 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
218 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
224 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min, NULL);
228 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max, NULL);
235 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
239 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max, NULL);
244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min, NULL);
248 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max, NULL);
253 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min, NULL);
257 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max, NULL);
268 int smu_v12_0_set_driver_table_location(struct smu_context *smu)
270 struct smu_table *driver_table = &smu->smu_table.driver_table;
274 ret = smu_cmn_send_smc_msg_with_param(smu,
279 ret = smu_cmn_send_smc_msg_with_param(smu,
314 int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu)
326 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
332 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu12\n");
341 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
342 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
343 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
344 smu->smu_table.boot_values.socclk = 0;
345 smu->smu_table.boot_values.dcefclk = 0;
346 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
347 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
348 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
349 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
350 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
351 smu->smu_table.boot_values.pp_table_id = 0;
352 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
358 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
359 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
360 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
361 smu->smu_table.boot_values.socclk = 0;
362 smu->smu_table.boot_values.dcefclk = 0;
363 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
364 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
365 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
366 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
367 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
368 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
369 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
372 smu->smu_table.boot_values.format_revision = header->format_revision;
373 smu->smu_table.boot_values.content_revision = header->content_revision;
375 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
378 &smu->smu_table.boot_values.socclk);
380 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
383 &smu->smu_table.boot_values.dcefclk);
385 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
388 &smu->smu_table.boot_values.vclk);
390 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
393 &smu->smu_table.boot_values.dclk);
395 if ((smu->smu_table.boot_values.format_revision == 3) &&
396 (smu->smu_table.boot_values.content_revision >= 2))
397 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
400 &smu->smu_table.boot_values.fclk);
402 smu_v12_0_atom_get_smu_clockinfo(smu->adev,
405 &smu->smu_table.boot_values.lclk);