swsmu/smu12/renoir_ppt.c

156 static int renoir_init_smc_tables(struct smu_context *smu)
158 	struct smu_table_context *smu_table = &smu->smu_table;
202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
205 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
250 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
280 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
289 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
293 			clock_limit = smu->smu_table.boot_values.uclk;
297 			clock_limit = smu->smu_table.boot_values.gfxclk;
300 			clock_limit = smu->smu_table.boot_values.socclk;
317 		ret = renoir_get_profiling_clk_mask(smu,
328 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
330 				dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
337 			ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
342 			ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
356 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
358 				dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
365 			ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
370 			ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
383 static int renoir_od_edit_dpm_table(struct smu_context *smu,
388 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
391 		dev_warn(smu->adev->dev,
399 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
404 			if (input[1] < smu->gfx_default_hard_min_freq) {
405 				dev_warn(smu->adev->dev,
407 					input[1], smu->gfx_default_hard_min_freq);
410 			smu->gfx_actual_hard_min_freq = input[1];
412 			if (input[1] > smu->gfx_default_soft_max_freq) {
413 				dev_warn(smu->adev->dev,
415 					input[1], smu->gfx_default_soft_max_freq);
418 			smu->gfx_actual_soft_max_freq = input[1];
425 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
428 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
429 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
433 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
436 			if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
437 				dev_err(smu->adev->dev,
439 					smu->gfx_actual_hard_min_freq,
440 					smu->gfx_actual_soft_max_freq);
444 			ret = smu_cmn_send_smc_msg_with_param(smu,
446 								smu->gfx_actual_hard_min_freq,
449 				dev_err(smu->adev->dev, "Set hard min sclk failed!");
453 			ret = smu_cmn_send_smc_msg_with_param(smu,
455 								smu->gfx_actual_soft_max_freq,
458 				dev_err(smu->adev->dev, "Set soft max sclk failed!");
470 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
475 	ret = smu_cmn_send_smc_msg_with_param(smu,
480 	ret = smu_cmn_send_smc_msg_with_param(smu,
486 	smu->gfx_default_hard_min_freq = min;
487 	smu->gfx_default_soft_max_freq = max;
488 	smu->gfx_actual_hard_min_freq = 0;
489 	smu->gfx_actual_soft_max_freq = 0;
494 static int renoir_print_clk_levels(struct smu_context *smu,
500 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
505 	ret = smu_cmn_get_metrics_table(smu, &metrics, false);
514 			ret = smu_cmn_send_smc_msg_with_param(smu,
519 			ret = smu_cmn_send_smc_msg_with_param(smu,
529 			min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
530 			max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
540 		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
598 			ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
620 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
623 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
650 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
656 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
657 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
662 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
663 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
672 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
677 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
678 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
683 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
684 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
693 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
707 		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
712 		ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
720 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
736 		if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
741 		ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
745 		ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
756 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
758 	DpmClocks_t *table = smu->smu_table.clocks_table;
797 static int renoir_force_clk_levels(struct smu_context *smu,
811 			dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
815 		ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
818 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
824 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
832 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
835 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
838 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
841 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
847 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
850 		ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
853 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
856 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
867 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
873 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
882 	workload_type = smu_cmn_to_asic_specific_index(smu,
890 		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
894 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
898 		dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
902 	smu->power_profile_mode = profile_mode;
907 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
912 	ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
916 	ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
920 	ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
924 	ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
931 static int renoir_set_performance_level(struct smu_context *smu,
939 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
940 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
942 		ret = renoir_force_dpm_limit_value(smu, true);
945 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
946 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
948 		ret = renoir_force_dpm_limit_value(smu, false);
951 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
952 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
954 		ret = renoir_unforce_dpm_levels(smu);
957 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
958 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
960 		ret = smu_cmn_send_smc_msg_with_param(smu,
966 		ret = smu_cmn_send_smc_msg_with_param(smu,
972 		ret = smu_cmn_send_smc_msg_with_param(smu,
978 		ret = smu_cmn_send_smc_msg_with_param(smu,
985 		ret = smu_cmn_send_smc_msg_with_param(smu,
991 		ret = smu_cmn_send_smc_msg_with_param(smu,
997 		ret = smu_cmn_send_smc_msg_with_param(smu,
1003 		ret = smu_cmn_send_smc_msg_with_param(smu,
1012 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1013 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1015 		ret = renoir_get_profiling_clk_mask(smu, level,
1021 		renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1022 		renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1023 		renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1026 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1027 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1029 		ret = renoir_set_peak_clock_by_device(smu);
1039 /* save watermark settings into pplib smu structure,
1040  * also pass data to smu controller
1043 		struct smu_context *smu,
1046 	Watermarks_t *table = smu->smu_table.watermarks_table;
1055 		/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1088 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
1091 	/* pass data to smu controller */
1092 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1093 	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1094 		ret = smu_cmn_write_watermarks_table(smu);
1096 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1099 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
1105 static int renoir_get_power_profile_mode(struct smu_context *smu,
1119 		workload_type = smu_cmn_to_asic_specific_index(smu,
1126 			i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1165 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1169 	struct smu_table_context *smu_table = &smu->smu_table;
1175 	struct amdgpu_device *adev = smu->adev;
1178 	ret = smu_cmn_get_metrics_table(smu,
1250 static int renoir_read_sensor(struct smu_context *smu,
1261 		ret = renoir_get_smu_metrics_data(smu,
1267 		ret = renoir_get_smu_metrics_data(smu,
1273 		ret = renoir_get_smu_metrics_data(smu,
1279 		ret = renoir_get_smu_metrics_data(smu,
1286 		ret = renoir_get_smu_metrics_data(smu,
1293 		ret = renoir_get_smu_metrics_data(smu,
1299 		ret = renoir_get_smu_metrics_data(smu,
1305 		ret = renoir_get_smu_metrics_data(smu,
1311 		ret = renoir_get_smu_metrics_data(smu,
1317 		ret = renoir_get_smu_metrics_data(smu,
1331 static bool renoir_is_dpm_running(struct smu_context *smu)
1333 	struct amdgpu_device *adev = smu->adev;
1347 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1350 	struct smu_table_context *smu_table = &smu->smu_table;
1356 	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1411 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1417 static int renoir_get_enabled_mask(struct smu_context *smu,
1468 void renoir_set_ppt_funcs(struct smu_context *smu)
1470 	struct amdgpu_device *adev = smu->adev;
1472 	smu->ppt_funcs = &renoir_ppt_funcs;
1473 	smu->message_map = renoir_message_map;
1474 	smu->clock_map = renoir_clk_map;
1475 	smu->table_map = renoir_table_map;
1476 	smu->workload_map = renoir_workload_map;
1477 	smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1478 	smu->is_apu = true;
1479 	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1480 	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1481 	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);