Lines Matching refs:smu
78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
80 (*member) = (smu->smu_table.driver_pptable + \
83 (*member) = (smu->smu_table.driver_pptable + \
96 static int get_table_size(struct smu_context *smu)
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
282 struct amdgpu_device *adev = smu->adev;
343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
353 if (smu->dc_controlled_by_gpio)
362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
364 struct smu_table_context *table_context = &smu->smu_table;
367 struct smu_baco_context *smu_baco = &smu->smu_baco;
368 struct amdgpu_device *adev = smu->adev;
396 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
398 struct smu_table_context *table_context = &smu->smu_table;
403 smu->adev->pm.no_fan =
405 if (smu->adev->pm.no_fan)
406 dev_info_once(smu->adev->dev,
410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
412 struct smu_table_context *table_context = &smu->smu_table;
417 smu->dc_controlled_by_gpio = true;
419 sienna_cichlid_check_bxco_support(smu);
420 sienna_cichlid_check_fan_support(smu);
427 * smu->od_settings just points to the actual overdrive_table
429 smu->od_settings = &powerplay_table->overdrive_table;
434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
442 ppt_beige_goby = smu->smu_table.driver_pptable;
444 ppt = smu->smu_table.driver_pptable;
449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
466 struct smu_table_context *table_context = &smu->smu_table;
471 table_size = get_table_size(smu);
478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
480 struct amdgpu_device *adev = smu->adev;
508 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
512 ret = smu_v11_0_setup_pptable(smu);
516 ret = sienna_cichlid_store_powerplay_table(smu);
520 ret = sienna_cichlid_append_powerplay_table(smu);
524 ret = sienna_cichlid_check_powerplay_table(smu);
528 return sienna_cichlid_patch_pptable_quirk(smu);
531 static int sienna_cichlid_tables_init(struct smu_context *smu)
533 struct smu_table_context *smu_table = &smu->smu_table;
537 table_size = get_table_size(smu);
595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
599 struct smu_table_context *smu_table= &smu->smu_table;
626 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
651 if (smu->od_enabled &&
661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
676 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
680 struct smu_table_context *smu_table = &smu->smu_table;
691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL);
730 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
734 struct smu_table_context *smu_table= &smu->smu_table;
748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
750 if (smu->smc_fw_version >= 0x3A4900)
752 else if (smu->smc_fw_version >= 0x3A4300)
756 if (smu->smc_fw_version >= 0x412D00)
760 if (smu->smc_fw_version >= 0x3B2300)
764 if (smu->smc_fw_version >= 0x491100)
771 ret = smu_cmn_get_metrics_table(smu,
887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
919 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
933 static void sienna_cichlid_stb_init(struct smu_context *smu);
935 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
937 struct amdgpu_device *adev = smu->adev;
940 ret = sienna_cichlid_tables_init(smu);
944 ret = sienna_cichlid_allocate_dpm_context(smu);
949 sienna_cichlid_stb_init(smu);
951 return smu_v11_0_init_smc_tables(smu);
954 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
958 struct amdgpu_device *adev = smu->adev;
965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
966 ret = smu_v11_0_set_single_dpm_table(smu,
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
984 ret = smu_v11_0_set_single_dpm_table(smu,
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1002 ret = smu_v11_0_set_single_dpm_table(smu,
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1020 ret = smu_v11_0_set_single_dpm_table(smu,
1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1064 ret = smu_v11_0_set_single_dpm_table(smu,
1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1083 ret = smu_v11_0_set_single_dpm_table(smu,
1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1101 ret = smu_v11_0_set_single_dpm_table(smu,
1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1119 ret = smu_v11_0_set_single_dpm_table(smu,
1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1137 ret = smu_v11_0_set_single_dpm_table(smu,
1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1155 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1157 struct amdgpu_device *adev = smu->adev;
1164 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1165 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1176 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1181 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1182 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1187 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1188 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1197 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1204 clk_id = smu_cmn_to_asic_specific_index(smu,
1242 return sienna_cichlid_get_smu_metrics_data(smu,
1248 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1255 clk_index = smu_cmn_to_asic_specific_index(smu,
1274 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1277 struct amdgpu_device *adev = smu->adev;
1278 struct smu_table_context *table_context = &smu->smu_table;
1279 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1283 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1307 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1311 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1315 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1317 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1325 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1328 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1350 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1371 if (!smu->od_enabled || !od_table || !od_settings)
1382 if (!smu->od_enabled || !od_table || !od_settings)
1393 if (!smu->od_enabled || !od_table || !od_settings)
1402 (smu->smc_fw_version < 0x003a2900))
1410 if (!smu->od_enabled || !od_table || !od_settings)
1442 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1459 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1464 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1468 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1472 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1477 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1487 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1490 smu->smu_dpm.dpm_context;
1498 &smu->pstate_table;
1499 struct amdgpu_device *adev = smu->adev;
1534 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1542 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1547 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1548 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1551 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1559 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1563 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1564 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1565 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1568 smu->display_config->num_display,
1578 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1583 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1590 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1601 return sienna_cichlid_get_smu_metrics_data(smu,
1606 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1611 smu->fan_max_rpm = *table_member;
1616 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1646 workload_type = smu_cmn_to_asic_specific_index(smu,
1652 result = smu_cmn_update_table(smu,
1656 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1661 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1709 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1717 smu->power_profile_mode = input[size];
1719 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1720 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1724 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1726 ret = smu_cmn_update_table(smu,
1730 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1770 ret = smu_cmn_update_table(smu,
1774 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1780 workload_type = smu_cmn_to_asic_specific_index(smu,
1782 smu->power_profile_mode);
1785 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1791 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1797 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1798 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1799 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1801 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1805 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1807 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1808 ret = smu_cmn_send_smc_msg_with_param(smu,
1813 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1818 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1822 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1823 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1825 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1833 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1836 Watermarks_t *table = smu->smu_table.watermarks_table;
1873 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1876 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1877 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1878 ret = smu_cmn_write_watermarks_table(smu);
1880 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1883 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1889 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1895 struct amdgpu_device *adev = smu->adev;
1907 ret = sienna_cichlid_get_smu_metrics_data(smu,
1913 ret = sienna_cichlid_get_smu_metrics_data(smu,
1919 ret = sienna_cichlid_get_smu_metrics_data(smu,
1925 ret = sienna_cichlid_get_smu_metrics_data(smu,
1931 ret = sienna_cichlid_get_smu_metrics_data(smu,
1937 ret = sienna_cichlid_get_smu_metrics_data(smu,
1943 ret = sienna_cichlid_get_smu_metrics_data(smu,
1950 ret = sienna_cichlid_get_smu_metrics_data(smu,
1957 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1963 ret = sienna_cichlid_get_smu_metrics_data(smu,
1973 ret = sienna_cichlid_get_smu_metrics_data(smu,
1989 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1991 struct amdgpu_device *adev = smu->adev;
1995 if (smu->smc_fw_version < 0x3A5300 ||
1996 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
1999 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
2001 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
2009 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2014 struct smu_table_context *table_context = &smu->smu_table;
2040 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2043 struct smu_table_context *table_context = &smu->smu_table;
2074 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2080 smu->smu_table.max_sustainable_clocks;
2081 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2084 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2088 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2090 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2093 smu->disable_uclk_switch = disable_memory_clock_switch;
2098 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2102 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2122 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2137 ret = smu_cmn_send_smc_msg_with_param(smu,
2148 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2152 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2155 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2158 struct amdgpu_device *adev = smu->adev;
2160 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2162 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2166 (smu->smc_fw_version < 0x003a2900)))
2167 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2170 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2173 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2175 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2177 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2181 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2184 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2188 sienna_cichlid_dump_od_table(smu, boot_od_table);
2196 if (!smu->adev->in_suspend) {
2198 smu->user_dpm_profile.user_od = false;
2199 } else if (smu->user_dpm_profile.user_od) {
2212 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2218 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2223 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2231 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2235 struct smu_table_context *table_context = &smu->smu_table;
2239 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2240 struct amdgpu_device *adev = smu->adev;
2245 if (!smu->od_enabled) {
2246 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2250 if (!smu->od_settings) {
2251 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2256 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2264 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2270 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2277 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2288 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2298 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2299 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2303 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2314 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2320 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2327 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2338 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2348 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2349 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2353 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2370 sienna_cichlid_dump_od_table(smu, od_table);
2371 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2373 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2377 smu->user_dpm_profile.user_od = true;
2382 smu->user_dpm_profile.user_od = false;
2388 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2398 (smu->smc_fw_version < 0x003a2900)) {
2399 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2406 sienna_cichlid_dump_od_table(smu, od_table);
2416 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2418 struct smu_table_context *table_context = &smu->smu_table;
2423 res = smu_v11_0_restore_user_od_settings(smu);
2430 static int sienna_cichlid_run_btc(struct smu_context *smu)
2434 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2436 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2441 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2443 struct amdgpu_device *adev = smu->adev;
2446 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2448 return smu_v11_0_baco_enter(smu);
2451 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2453 struct amdgpu_device *adev = smu->adev;
2458 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2460 return smu_v11_0_baco_exit(smu);
2464 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2466 struct amdgpu_device *adev = smu->adev;
2475 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2490 static void beige_goby_dump_pptable(struct smu_context *smu)
2492 struct smu_table_context *table_context = &smu->smu_table;
2496 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2498 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2499 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2500 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2503 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2504 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2505 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2506 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2510 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2511 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2515 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2518 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2519 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2520 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2521 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2522 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2524 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2526 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2527 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2529 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2531 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2533 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2534 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2535 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2536 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2538 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2540 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2542 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2543 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2544 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2545 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2547 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2548 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2550 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2551 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2552 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2553 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2554 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2555 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2556 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2557 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2559 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2580 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2601 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2622 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2643 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2664 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2685 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2706 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2727 dev_info(smu->adev->dev, "FreqTableGfx\n");
2729 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2731 dev_info(smu->adev->dev, "FreqTableVclk\n");
2733 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2735 dev_info(smu->adev->dev, "FreqTableDclk\n");
2737 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2739 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2741 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2743 dev_info(smu->adev->dev, "FreqTableUclk\n");
2745 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2747 dev_info(smu->adev->dev, "FreqTableFclk\n");
2749 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2751 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2752 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2753 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2754 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2755 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2756 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2757 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2758 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2759 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2761 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2763 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2765 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2766 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2768 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2770 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2772 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2774 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2776 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2778 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2780 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2782 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2784 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2785 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2786 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2787 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2788 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2790 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2792 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2793 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2794 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2795 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2796 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2797 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2798 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2799 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2800 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2801 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2802 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2804 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2805 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2806 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2807 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2808 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2809 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2811 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2812 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2813 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2814 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2815 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2817 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2819 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2821 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2822 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2823 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2824 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2826 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2828 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2830 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2831 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2833 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2835 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2836 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2838 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2840 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2841 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2843 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2845 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2847 dev_info(smu->adev->dev, "PcieLaneCount\n");
2849 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2851 dev_info(smu->adev->dev, "LclkFreq\n");
2853 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2855 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2856 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2858 dev_info(smu->adev->dev, "FanGain\n");
2860 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2862 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2863 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2864 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2865 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2866 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2867 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2868 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2869 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2870 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2871 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2872 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2873 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2875 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2876 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2877 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2878 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2880 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2881 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2882 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2883 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2885 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2889 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2893 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2897 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2901 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2905 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2908 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2912 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2914 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2916 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2920 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2924 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2929 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2930 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2932 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2933 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2934 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2935 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2937 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2938 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2939 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2940 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2942 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2943 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2945 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2947 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2948 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2949 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2951 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2952 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2956 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2960 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2964 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2969 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2970 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2971 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2972 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2973 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2974 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2975 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2976 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2978 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2979 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2980 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2981 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2982 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2983 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2986 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2987 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2989 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2991 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2993 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2995 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2997 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2999 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3001 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3005 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3006 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3007 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3008 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3010 dev_info(smu->adev->dev, "Board Parameters:\n");
3011 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3012 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3013 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3014 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3015 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3016 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3017 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3018 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3020 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3021 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3022 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3024 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3025 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3026 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3028 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3029 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3030 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3032 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3033 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3034 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3036 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3038 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3039 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3040 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3041 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3042 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3043 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3044 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3045 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3046 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3047 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3048 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3049 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3050 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3051 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3052 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3053 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3055 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3056 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3057 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3059 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3060 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3061 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3063 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3064 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3066 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3067 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3068 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3070 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3071 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3072 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3073 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3074 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3076 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3077 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3079 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3081 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3082 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3084 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3085 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3087 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3088 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3090 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3092 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3093 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3094 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3095 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3097 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3098 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3099 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3100 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3101 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3102 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3103 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3104 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3105 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3106 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3107 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3109 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3110 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3111 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3112 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3113 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3114 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3115 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3116 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3119 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3121 struct smu_table_context *table_context = &smu->smu_table;
3125 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3127 beige_goby_dump_pptable(smu);
3131 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3133 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3134 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3135 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3138 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3139 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3140 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3141 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3145 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3146 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3150 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3153 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3154 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3155 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3156 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3157 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3159 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3161 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3162 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3164 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3166 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3168 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3169 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3170 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3171 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3173 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3174 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3176 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3177 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3178 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3179 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3181 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3182 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3183 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3184 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3186 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3187 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3189 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3190 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3191 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3192 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3193 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3194 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3195 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3196 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3198 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3219 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3240 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3261 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3282 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3303 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3324 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3345 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3366 dev_info(smu->adev->dev, "FreqTableGfx\n");
3368 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3370 dev_info(smu->adev->dev, "FreqTableVclk\n");
3372 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3374 dev_info(smu->adev->dev, "FreqTableDclk\n");
3376 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3378 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3380 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3382 dev_info(smu->adev->dev, "FreqTableUclk\n");
3384 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3386 dev_info(smu->adev->dev, "FreqTableFclk\n");
3388 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3390 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3391 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3392 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3393 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3394 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3395 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3396 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3397 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3398 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3400 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3402 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3404 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3405 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3407 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3409 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3411 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3413 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3415 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3419 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3421 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3423 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3424 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3425 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3426 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3427 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3429 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3431 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3432 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3433 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3434 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3435 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3436 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3437 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3438 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3439 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3440 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3441 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3443 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3444 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3445 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3446 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3447 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3448 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3450 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3451 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3452 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3453 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3454 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3456 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3458 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3460 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3461 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3462 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3463 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3465 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3467 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3469 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3470 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3472 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3474 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3475 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3477 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3479 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3480 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3482 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3484 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3486 dev_info(smu->adev->dev, "PcieLaneCount\n");
3488 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3490 dev_info(smu->adev->dev, "LclkFreq\n");
3492 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3494 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3495 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3497 dev_info(smu->adev->dev, "FanGain\n");
3499 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3501 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3502 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3503 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3504 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3505 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3506 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3507 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3508 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3509 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3510 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3511 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3512 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3514 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3515 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3516 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3517 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3519 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3520 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3521 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3522 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3524 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3528 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3532 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3536 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3540 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3544 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3547 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3551 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3553 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3555 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3559 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3563 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3568 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3569 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3571 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3572 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3573 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3574 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3576 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3577 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3578 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3579 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3581 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3582 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3584 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3586 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3587 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3588 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3590 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3591 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3595 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3599 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3603 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3608 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3609 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3610 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3611 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3612 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3613 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3614 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3615 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3617 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3618 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3619 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3620 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3621 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3622 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3625 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3626 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3628 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3630 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3632 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3634 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3636 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3638 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3640 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3644 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3645 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3646 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3647 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3649 dev_info(smu->adev->dev, "Board Parameters:\n");
3650 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3651 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3652 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3653 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3654 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3655 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3656 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3657 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3659 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3660 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3661 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3663 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3664 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3665 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3667 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3668 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3669 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3671 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3672 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3673 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3675 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3677 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3678 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3679 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3680 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3681 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3682 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3683 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3684 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3685 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3686 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3687 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3688 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3689 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3690 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3691 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3692 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3694 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3695 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3696 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3698 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3699 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3700 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3702 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3703 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3705 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3706 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3707 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3709 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3710 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3711 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3712 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3713 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3715 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3716 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3718 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3720 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3721 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3723 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3724 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3726 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3727 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3729 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3731 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3732 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3733 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3734 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3736 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3737 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3738 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3739 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3740 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3741 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3742 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3743 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3744 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3745 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3746 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3748 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3749 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3750 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3751 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3752 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3753 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3754 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3755 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3763 struct smu_context *smu = adev->powerplay.pp_handle;
3764 struct smu_table_context *smu_table = &smu->smu_table;
3814 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3855 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3857 struct amdgpu_device *adev = smu->adev;
3897 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3899 struct amdgpu_device *adev = smu->adev;
3912 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3915 struct smu_table_context *smu_table = &smu->smu_table;
3925 struct amdgpu_device *adev = smu->adev;
3931 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3933 if (smu->smc_fw_version >= 0x3A4900)
3935 else if (smu->smc_fw_version >= 0x3A4300)
3939 if (smu->smc_fw_version >= 0x412D00)
3943 if (smu->smc_fw_version >= 0x3B2300)
3947 if (smu->smc_fw_version >= 0x491100)
3954 ret = smu_cmn_get_metrics_table(smu,
4039 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4048 smu->smc_fw_version > 0x003A1E00) ||
4050 smu->smc_fw_version > 0x00410400)) {
4057 smu_v11_0_get_current_pcie_link_width(smu);
4059 smu_v11_0_get_current_pcie_link_speed(smu);
4069 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4073 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
4079 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4082 struct smu_table_context *smu_table = &smu->smu_table;
4088 ret = sienna_cichlid_check_ecc_table_support(smu);
4092 ret = smu_cmn_update_table(smu,
4098 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4118 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4130 return smu_cmn_send_smc_msg_with_param(smu,
4136 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4142 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4145 if (smu->smc_fw_version < 0x003a2500) {
4146 ret = smu_cmn_send_smc_msg_with_param(smu,
4151 ret = smu_cmn_send_smc_msg_with_param(smu,
4157 if (smu->smc_fw_version < 0x003a2500) {
4158 ret = smu_cmn_send_smc_msg_with_param(smu,
4163 ret = smu_cmn_send_smc_msg_with_param(smu,
4174 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4180 if (smu->smc_fw_version < 0x003A2D00)
4183 return smu_cmn_send_smc_msg_with_param(smu,
4185 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4190 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4196 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4201 return smu_v11_0_system_features_control(smu, en);
4204 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4211 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4221 static void sienna_cichlid_stb_init(struct smu_context *smu)
4223 struct amdgpu_device *adev = smu->adev;
4227 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4230 if (!smu->stb_context.enabled)
4233 spin_lock_init(&smu->stb_context.lock);
4237 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4238 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4240 dev_info(smu->adev->dev, "STB initialized to %d entries",
4241 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4245 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4248 struct amdgpu_device *adev = smu->adev;
4266 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4290 return smu_cmn_update_table(smu,
4297 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4302 struct amdgpu_device *adev = smu->adev;
4305 spin_lock(&smu->stb_context.lock);
4315 spin_unlock(&smu->stb_context.lock);
4320 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4325 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4328 struct amdgpu_device *adev = smu->adev;
4331 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4334 mutex_lock(&smu->message_lock);
4336 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4339 ret = smu_cmn_wait_for_response(smu);
4341 ret = smu_cmn_wait_for_response(smu);
4359 dev_info(smu->adev->dev, "restore config space...\n");
4363 mutex_unlock(&smu->message_lock);
4465 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4467 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4468 smu->message_map = sienna_cichlid_message_map;
4469 smu->clock_map = sienna_cichlid_clk_map;
4470 smu->feature_map = sienna_cichlid_feature_mask_map;
4471 smu->table_map = sienna_cichlid_table_map;
4472 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4473 smu->workload_map = sienna_cichlid_workload_map;
4474 smu_v11_0_set_smu_mailbox_registers(smu);