Lines Matching defs:pptable
399 PPTable_t *pptable = table_context->driver_pptable;
400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
2493 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2498 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2499 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2500 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2503 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2504 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2505 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2506 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2510 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2511 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2515 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2518 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2519 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2520 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2521 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2522 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2524 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2526 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2527 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2529 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2531 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2533 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2534 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2535 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2536 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2538 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2540 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2542 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2543 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2544 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2545 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2547 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2548 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2550 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2551 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2552 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2553 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2554 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2555 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2556 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2557 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2568 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2569 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2570 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2571 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2572 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2573 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2574 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2575 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2576 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2577 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2578 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2589 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2590 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2591 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2592 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2593 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2594 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2595 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2596 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2597 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2598 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2599 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2610 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2611 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2612 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2613 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2614 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2615 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2616 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2617 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2618 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2619 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2620 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2631 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2632 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2633 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2634 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2635 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2636 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2637 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2638 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2639 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2640 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2641 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2652 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2653 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2654 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2655 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2656 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2657 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2658 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2659 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2660 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2661 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2662 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2673 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2674 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2675 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2676 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2677 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2678 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2679 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2680 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2681 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2682 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2683 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2694 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2695 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2696 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2697 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2698 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2699 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2700 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2701 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2702 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2703 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2704 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2715 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2716 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2717 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2718 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2719 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2720 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2721 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2722 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2723 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2724 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2725 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2729 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2733 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2737 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2741 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2745 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2749 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2752 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2753 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2754 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2755 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2756 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2757 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2758 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2759 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2763 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2765 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2766 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2770 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2774 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2778 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2782 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2784 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2785 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2786 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2787 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2788 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2790 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2792 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2793 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2794 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2795 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2796 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2797 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2798 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2799 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2800 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2801 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2802 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2804 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2805 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2806 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2807 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2808 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2809 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2811 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2812 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2813 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2814 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2815 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2819 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2821 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2822 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2823 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2824 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2828 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2832 pptable->UclkDpmSrcFreqRange.Fmin);
2834 pptable->UclkDpmSrcFreqRange.Fmax);
2837 pptable->UclkDpmTargFreqRange.Fmin);
2839 pptable->UclkDpmTargFreqRange.Fmax);
2840 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2841 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2845 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2849 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2853 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2855 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2856 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2860 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2862 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2863 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2864 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2865 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2866 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2867 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2868 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2869 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2870 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2871 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2872 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2873 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2875 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2876 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2877 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2878 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2880 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2881 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2882 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2883 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2886 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2887 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2888 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2890 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2891 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2892 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2894 pptable->dBtcGbGfxPll.a,
2895 pptable->dBtcGbGfxPll.b,
2896 pptable->dBtcGbGfxPll.c);
2898 pptable->dBtcGbGfxDfll.a,
2899 pptable->dBtcGbGfxDfll.b,
2900 pptable->dBtcGbGfxDfll.c);
2902 pptable->dBtcGbSoc.a,
2903 pptable->dBtcGbSoc.b,
2904 pptable->dBtcGbSoc.c);
2906 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2907 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2909 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2910 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2915 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2917 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2921 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2922 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2923 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2925 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2926 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2927 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2929 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2930 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2932 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2933 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2934 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2935 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2937 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2938 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2939 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2940 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2942 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2943 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2947 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2948 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2949 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2951 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2953 pptable->ReservedEquation0.a,
2954 pptable->ReservedEquation0.b,
2955 pptable->ReservedEquation0.c);
2957 pptable->ReservedEquation1.a,
2958 pptable->ReservedEquation1.b,
2959 pptable->ReservedEquation1.c);
2961 pptable->ReservedEquation2.a,
2962 pptable->ReservedEquation2.b,
2963 pptable->ReservedEquation2.c);
2965 pptable->ReservedEquation3.a,
2966 pptable->ReservedEquation3.b,
2967 pptable->ReservedEquation3.c);
2969 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2970 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2971 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2972 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2973 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2974 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2975 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2976 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2978 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2979 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2980 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2981 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2982 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2983 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2988 pptable->I2cControllers[i].Enabled);
2990 pptable->I2cControllers[i].Speed);
2992 pptable->I2cControllers[i].SlaveAddress);
2994 pptable->I2cControllers[i].ControllerPort);
2996 pptable->I2cControllers[i].ControllerName);
2998 pptable->I2cControllers[i].ThermalThrotter);
3000 pptable->I2cControllers[i].I2cProtocol);
3002 pptable->I2cControllers[i].PaddingConfig);
3005 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3006 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3007 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3008 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3011 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3012 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3013 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3014 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3015 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3016 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3017 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3018 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3020 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3021 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3022 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3024 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3025 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3026 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3028 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3029 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3030 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3032 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3033 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3034 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3036 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3038 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3039 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3040 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3041 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3042 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3043 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3044 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3045 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3046 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3047 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3048 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3049 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3050 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3051 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3052 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3053 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3055 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3056 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3057 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3059 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3060 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3061 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3063 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3064 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3066 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3067 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3068 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3070 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3071 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3072 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3073 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3074 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3076 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3077 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3081 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3084 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3087 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3090 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3092 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3093 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3094 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3095 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3097 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3098 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3099 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3100 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3101 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3102 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3103 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3104 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3105 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3106 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3107 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3109 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3110 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3111 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3112 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3113 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3114 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3115 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3116 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3122 PPTable_t *pptable = table_context->driver_pptable;
3133 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3134 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3135 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3138 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3139 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3140 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3141 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3145 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3146 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3150 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3153 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3154 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3155 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3156 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3157 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3159 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3161 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3162 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3164 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3166 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3168 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3169 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3170 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3171 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3173 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3174 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3176 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3177 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3178 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3179 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3181 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3182 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3183 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3184 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3186 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3187 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3189 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3190 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3191 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3192 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3193 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3194 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3195 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3196 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3207 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3208 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3209 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3210 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3211 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3212 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3213 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3214 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3215 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3216 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3217 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3228 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3229 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3230 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3231 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3232 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3233 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3234 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3235 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3236 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3237 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3238 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3249 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3250 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3251 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3252 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3253 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3254 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3255 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3256 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3257 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3258 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3259 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3270 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3271 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3272 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3273 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3274 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3275 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3276 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3277 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3278 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3279 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3280 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3291 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3292 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3293 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3294 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3295 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3296 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3297 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3298 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3299 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3300 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3301 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3312 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3313 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3314 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3315 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3316 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3317 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3318 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3319 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3320 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3321 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3322 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3333 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3334 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3335 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3336 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3337 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3338 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3339 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3340 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3341 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3342 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3343 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3354 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3355 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3356 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3357 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3358 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3359 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3360 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3361 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3362 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3363 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3364 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3368 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3372 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3376 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3380 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3384 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3388 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3391 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3392 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3393 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3394 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3395 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3396 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3397 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3398 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3402 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3404 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3405 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3409 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3413 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3421 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3423 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3424 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3425 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3426 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3427 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3429 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3431 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3432 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3433 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3434 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3435 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3436 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3437 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3438 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3439 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3440 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3441 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3443 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3444 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3445 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3446 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3447 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3448 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3450 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3451 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3452 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3453 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3454 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3458 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3460 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3461 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3462 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3463 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3467 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3471 pptable->UclkDpmSrcFreqRange.Fmin);
3473 pptable->UclkDpmSrcFreqRange.Fmax);
3476 pptable->UclkDpmTargFreqRange.Fmin);
3478 pptable->UclkDpmTargFreqRange.Fmax);
3479 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3480 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3484 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3488 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3492 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3494 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3495 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3499 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3501 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3502 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3503 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3504 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3505 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3506 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3507 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3508 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3509 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3510 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3511 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3512 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3514 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3515 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3516 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3517 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3519 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3520 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3521 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3522 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3525 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3526 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3527 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3529 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3530 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3531 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3533 pptable->dBtcGbGfxPll.a,
3534 pptable->dBtcGbGfxPll.b,
3535 pptable->dBtcGbGfxPll.c);
3537 pptable->dBtcGbGfxDfll.a,
3538 pptable->dBtcGbGfxDfll.b,
3539 pptable->dBtcGbGfxDfll.c);
3541 pptable->dBtcGbSoc.a,
3542 pptable->dBtcGbSoc.b,
3543 pptable->dBtcGbSoc.c);
3545 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3546 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3548 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3549 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3554 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3556 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3560 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3561 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3562 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3564 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3565 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3566 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3568 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3569 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3571 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3572 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3573 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3574 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3576 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3577 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3578 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3579 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3581 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3582 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3586 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3587 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3588 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3590 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3592 pptable->ReservedEquation0.a,
3593 pptable->ReservedEquation0.b,
3594 pptable->ReservedEquation0.c);
3596 pptable->ReservedEquation1.a,
3597 pptable->ReservedEquation1.b,
3598 pptable->ReservedEquation1.c);
3600 pptable->ReservedEquation2.a,
3601 pptable->ReservedEquation2.b,
3602 pptable->ReservedEquation2.c);
3604 pptable->ReservedEquation3.a,
3605 pptable->ReservedEquation3.b,
3606 pptable->ReservedEquation3.c);
3608 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3609 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3610 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3611 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3612 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3613 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3614 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3615 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3617 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3618 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3619 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3620 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3621 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3622 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3627 pptable->I2cControllers[i].Enabled);
3629 pptable->I2cControllers[i].Speed);
3631 pptable->I2cControllers[i].SlaveAddress);
3633 pptable->I2cControllers[i].ControllerPort);
3635 pptable->I2cControllers[i].ControllerName);
3637 pptable->I2cControllers[i].ThermalThrotter);
3639 pptable->I2cControllers[i].I2cProtocol);
3641 pptable->I2cControllers[i].PaddingConfig);
3644 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3645 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3646 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3647 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3650 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3651 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3652 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3653 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3654 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3655 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3656 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3657 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3659 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3660 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3661 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3663 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3664 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3665 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3667 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3668 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3669 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3671 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3672 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3673 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3675 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3677 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3678 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3679 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3680 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3681 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3682 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3683 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3684 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3685 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3686 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3687 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3688 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3689 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3690 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3691 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3692 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3694 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3695 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3696 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3698 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3699 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3700 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3702 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3703 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3705 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3706 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3707 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3709 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3710 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3711 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3712 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3713 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3715 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3716 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3720 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3723 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3726 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3729 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3731 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3732 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3733 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3734 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3736 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3737 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3738 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3739 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3740 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3741 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3742 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3743 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3744 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3745 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3746 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3748 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3749 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3750 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3751 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3752 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3753 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3754 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3755 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);