swsmu/smu11/navi10_ppt.c

941 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
943 	if (!smu_dpm->dpm_context)
968 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
974 	dpm_table = &dpm_context->dpm_tables.soc_table;
992 	dpm_table = &dpm_context->dpm_tables.gfx_table;
1010 	dpm_table = &dpm_context->dpm_tables.uclk_table;
1028 	dpm_table = &dpm_context->dpm_tables.vclk_table;
1046 	dpm_table = &dpm_context->dpm_tables.dclk_table;
1064 	dpm_table = &dpm_context->dpm_tables.dcef_table;
1082 	dpm_table = &dpm_context->dpm_tables.pixel_table;
1100 	dpm_table = &dpm_context->dpm_tables.display_table;
1118 	dpm_table = &dpm_context->dpm_tables.phy_table;
1265 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1337 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1338 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1339 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1340 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1341 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1342 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1343 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1344 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1345 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1346 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1348 					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1349 					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1472 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1537 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1538 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1539 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1540 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1541 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1542 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1543 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1544 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1545 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1546 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1548 					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1549 					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1698 	struct smu_11_0_dpm_context *dpm_context =
1699 				smu->smu_dpm.dpm_context;
1701 				&dpm_context->dpm_tables.gfx_table;
1703 				&dpm_context->dpm_tables.uclk_table;
1705 				&dpm_context->dpm_tables.soc_table;
2390 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2397 		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2398 		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2415 			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2417 			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;