swsmu/smu11/arcturus_ppt.c

250 static int arcturus_tables_init(struct smu_context *smu)
252 	struct smu_table_context *smu_table = &smu->smu_table;
286 static int arcturus_allocate_dpm_context(struct smu_context *smu)
288 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
299 static int arcturus_init_smc_tables(struct smu_context *smu)
303 	ret = arcturus_tables_init(smu);
307 	ret = arcturus_allocate_dpm_context(smu);
311 	return smu_v11_0_init_smc_tables(smu);
315 arcturus_get_allowed_feature_mask(struct smu_context *smu,
327 static int arcturus_set_default_dpm_table(struct smu_context *smu)
329 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
330 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
336 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
337 		ret = smu_v11_0_set_single_dpm_table(smu,
346 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
354 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
355 		ret = smu_v11_0_set_single_dpm_table(smu,
364 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
372 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
373 		ret = smu_v11_0_set_single_dpm_table(smu,
382 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
390 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
391 		ret = smu_v11_0_set_single_dpm_table(smu,
400 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
409 static void arcturus_check_bxco_support(struct smu_context *smu)
411 	struct smu_table_context *table_context = &smu->smu_table;
414 	struct smu_baco_context *smu_baco = &smu->smu_baco;
415 	struct amdgpu_device *adev = smu->adev;
427 static void arcturus_check_fan_support(struct smu_context *smu)
429 	struct smu_table_context *table_context = &smu->smu_table;
433 	smu->adev->pm.no_fan =
435 	if (smu->adev->pm.no_fan)
436 		dev_info_once(smu->adev->dev,
440 static int arcturus_check_powerplay_table(struct smu_context *smu)
442 	struct smu_table_context *table_context = &smu->smu_table;
446 	arcturus_check_bxco_support(smu);
447 	arcturus_check_fan_support(smu);
455 static int arcturus_store_powerplay_table(struct smu_context *smu)
457 	struct smu_table_context *table_context = &smu->smu_table;
467 static int arcturus_append_powerplay_table(struct smu_context *smu)
469 	struct smu_table_context *table_context = &smu->smu_table;
477 	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
482 	dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
493 static int arcturus_setup_pptable(struct smu_context *smu)
497 	ret = smu_v11_0_setup_pptable(smu);
501 	ret = arcturus_store_powerplay_table(smu);
505 	ret = arcturus_append_powerplay_table(smu);
509 	ret = arcturus_check_powerplay_table(smu);
516 static int arcturus_run_btc(struct smu_context *smu)
520 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
522 		dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
526 	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
529 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
532 				smu->smu_dpm.dpm_context;
540 				&smu->pstate_table;
572 static void arcturus_get_clk_table(struct smu_context *smu,
595 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
599 	struct smu_table_context *smu_table = &smu->smu_table;
603 	ret = smu_cmn_get_metrics_table(smu,
693 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
703 	clk_id = smu_cmn_to_asic_specific_index(smu,
717 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
723 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
729 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
735 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
741 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
753 	return arcturus_get_smu_metrics_data(smu,
758 static int arcturus_emit_clk_levels(struct smu_context *smu,
764 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
781 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
783 			dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
788 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
793 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
795 			dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
800 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
805 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
807 			dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
812 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
817 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
819 			dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
824 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
829 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
831 			dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
836 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
841 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
843 			dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
848 		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
853 		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
854 		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
895 				smu->smu_table.boot_values.lclk / 100);
905 static int arcturus_upload_dpm_level(struct smu_context *smu,
911 			smu->smu_dpm.dpm_context;
915 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
918 		ret = smu_cmn_send_smc_msg_with_param(smu,
923 			dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
929 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
932 		ret = smu_cmn_send_smc_msg_with_param(smu,
937 			dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
943 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
946 		ret = smu_cmn_send_smc_msg_with_param(smu,
951 			dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
960 static int arcturus_force_clk_levels(struct smu_context *smu,
963 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
968 	if ((smu->smc_fw_version >= 0x361200) &&
969 	    (smu->smc_fw_version <= 0x361a00)) {
970 		dev_err(smu->adev->dev, "Forcing clock level is not supported with "
982 			dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
988 		ret = arcturus_upload_dpm_level(smu,
993 			dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
997 		ret = arcturus_upload_dpm_level(smu,
1002 			dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1023 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1026 	struct smu_table_context *table_context = &smu->smu_table;
1029 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1053 static int arcturus_read_sensor(struct smu_context *smu,
1057 	struct smu_table_context *table_context = &smu->smu_table;
1073 		ret = arcturus_get_smu_metrics_data(smu,
1079 		ret = arcturus_get_smu_metrics_data(smu,
1085 		ret = arcturus_get_smu_metrics_data(smu,
1091 		ret = arcturus_get_smu_metrics_data(smu,
1097 		ret = arcturus_get_smu_metrics_data(smu,
1103 		ret = arcturus_get_smu_metrics_data(smu,
1109 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1115 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1120 		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1132 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1135 	struct amdgpu_device *adev = smu->adev;
1147 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1150 	struct amdgpu_device *adev = smu->adev;
1159 	switch (smu_v11_0_get_fan_control_mode(smu)) {
1161 		ret = arcturus_get_smu_metrics_data(smu,
1171 		if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1172 		     && !smu->user_dpm_profile.fan_speed_rpm) {
1192 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1195 	struct amdgpu_device *adev = smu->adev;
1214 	return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1217 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1220 	struct amdgpu_device *adev = smu->adev;
1234 	return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1237 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1240 	struct amdgpu_device *adev = smu->adev;
1249 	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1250 	     && !smu->user_dpm_profile.fan_speed_pwm) {
1271 static int arcturus_get_fan_parameters(struct smu_context *smu)
1273 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1275 	smu->fan_max_rpm = pptable->FanMaximumRpm;
1280 static int arcturus_get_power_limit(struct smu_context *smu,
1286 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1289 	if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1292 			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1311 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1334 	if (smu->smc_fw_version >= 0x360d00)
1347 		workload_type = smu_cmn_to_asic_specific_index(smu,
1353 		if (smu->smc_fw_version >= 0x360d00) {
1354 			result = smu_cmn_update_table(smu,
1360 				dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1366 			i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1368 		if (smu->smc_fw_version >= 0x360d00) {
1402 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1412 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1418 	     (smu->smc_fw_version >= 0x360d00)) {
1419 		ret = smu_cmn_update_table(smu,
1425 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1454 		ret = smu_cmn_update_table(smu,
1460 			dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1469 	workload_type = smu_cmn_to_asic_specific_index(smu,
1473 		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1477 	ret = smu_cmn_send_smc_msg_with_param(smu,
1482 		dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1486 	smu->power_profile_mode = profile_mode;
1491 static int arcturus_set_performance_level(struct smu_context *smu,
1501 		if ((smu->smc_fw_version >= 0x361200) &&
1502 		    (smu->smc_fw_version <= 0x361a00)) {
1503 			dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1512 	return smu_v11_0_set_performance_level(smu, level);
1515 static void arcturus_dump_pptable(struct smu_context *smu)
1517 	struct smu_table_context *table_context = &smu->smu_table;
1521 	dev_info(smu->adev->dev, "Dumped PPTable:\n");
1523 	dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1525 	dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1526 	dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1529 		dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1530 		dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1533 	dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1534 	dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1535 	dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1536 	dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1538 	dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1539 	dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1540 	dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1541 	dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1542 	dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1543 	dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1544 	dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1546 	dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1547 	dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1549 	dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1551 	dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1552 	dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1554 	dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1555 	dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1556 	dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1557 	dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1559 	dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1560 	dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1561 	dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1562 	dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1564 	dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1565 	dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1567 	dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1588 	dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1609 	dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1630 	dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1651 	dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1672 	dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1694 	dev_info(smu->adev->dev, "FreqTableGfx\n");
1696 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1698 	dev_info(smu->adev->dev, "FreqTableVclk\n");
1700 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1702 	dev_info(smu->adev->dev, "FreqTableDclk\n");
1704 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1706 	dev_info(smu->adev->dev, "FreqTableSocclk\n");
1708 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1710 	dev_info(smu->adev->dev, "FreqTableUclk\n");
1712 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1714 	dev_info(smu->adev->dev, "FreqTableFclk\n");
1716 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1718 	dev_info(smu->adev->dev, "Mp0clkFreq\n");
1720 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1722 	dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1724 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1726 	dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1727 	dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1728 	dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1729 	dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1730 	dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1731 	dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1732 	dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1733 	dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1734 	dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1736 	dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1737 	dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1738 	dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1739 	dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1741 	dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1742 	dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1744 	dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1745 	dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1746 	dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1747 	dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1748 	dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1749 	dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1751 	dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1752 	dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1753 	dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1754 	dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1755 	dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1756 	dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1757 	dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1758 	dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1759 	dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1761 	dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1762 	dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1763 	dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1764 	dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1766 	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1767 	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1768 	dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1769 	dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1771 	dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1775 	dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1779 	dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1784 	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1787 	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1791 	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1795 	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1800 	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1801 	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1803 	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1804 	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1805 	dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1806 	dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1808 	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1809 	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1810 	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1811 	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1813 	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1814 	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1816 	dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1818 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1819 	dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1820 	dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1822 	dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1823 	dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1824 	dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1825 	dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1826 	dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1827 	dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1828 	dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1829 	dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1831 	dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1832 	dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1836 	dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1840 	dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1844 	dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1849 	dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1850 	dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1852 	dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1853 	dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1854 	dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1856 	dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1857 	dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1859 	dev_info(smu->adev->dev, "Board Parameters:\n");
1860 	dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1861 	dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1863 	dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1864 	dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1865 	dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1866 	dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1868 	dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1869 	dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1871 	dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1872 	dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1873 	dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1875 	dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1876 	dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1877 	dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1879 	dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1880 	dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1881 	dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1883 	dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1884 	dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1885 	dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1887 	dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1888 	dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1889 	dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1890 	dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1892 	dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1893 	dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1894 	dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1896 	dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1897 	dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1898 	dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1900 	dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1901 	dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1902 	dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1904 	dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1905 	dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1906 	dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1909 		dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1910 		dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1912 		dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1914 		dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1916 		dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1918 		dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1920 		dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1922 		dev_info(smu->adev->dev, "                   .Speed = %d\n",
1926 	dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1927 	dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1929 	dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1931 	dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1933 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1934 	dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1936 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1937 	dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1939 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1940 	dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1942 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1946 static bool arcturus_is_dpm_running(struct smu_context *smu)
1951 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1958 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1963 		if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1964 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
1966 				dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1971 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1972 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
1974 				dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1988 	struct smu_context *smu = adev->powerplay.pp_handle;
1989 	struct smu_table_context *smu_table = &smu->smu_table;
2039 	r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2081 static int arcturus_i2c_control_init(struct smu_context *smu)
2083 	struct amdgpu_device *adev = smu->adev;
2122 static void arcturus_i2c_control_fini(struct smu_context *smu)
2124 	struct amdgpu_device *adev = smu->adev;
2137 static void arcturus_get_unique_id(struct smu_context *smu)
2139 	struct amdgpu_device *adev = smu->adev;
2144 	if (smu->smc_fw_version < 0x361700) {
2150 	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2151 	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2157 static int arcturus_set_df_cstate(struct smu_context *smu,
2160 	struct amdgpu_device *adev = smu->adev;
2170 	if (smu->smc_fw_version < 0x360F00) {
2171 		dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2175 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2178 static int arcturus_select_xgmi_plpd_policy(struct smu_context *smu,
2182 	if (smu->smc_fw_version < 0x00361700) {
2183 		dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2188 		return smu_cmn_send_smc_msg_with_param(smu,
2192 		return smu_cmn_send_smc_msg_with_param(smu,
2211 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2215 	struct amdgpu_device *adev = smu->adev;
2219 	ret = arcturus_get_smu_metrics_data(smu,
2245 	kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2250 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2252 	struct amdgpu_device *adev = smu->adev;
2260 	return smu_v11_0_get_current_pcie_link_speed(smu);
2263 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2266 	struct smu_table_context *smu_table = &smu->smu_table;
2272 	ret = smu_cmn_get_metrics_table(smu,
2314 			smu_v11_0_get_current_pcie_link_width(smu);
2316 			arcturus_get_current_pcie_link_speed(smu);
2409 void arcturus_set_ppt_funcs(struct smu_context *smu)
2411 	smu->ppt_funcs = &arcturus_ppt_funcs;
2412 	smu->message_map = arcturus_message_map;
2413 	smu->clock_map = arcturus_clk_map;
2414 	smu->feature_map = arcturus_feature_mask_map;
2415 	smu->table_map = arcturus_table_map;
2416 	smu->pwr_src_map = arcturus_pwr_src_map;
2417 	smu->workload_map = arcturus_workload_map;
2418 	smu_v11_0_set_smu_mailbox_registers(smu);