Lines Matching defs:hwmgr
82 static int vegam_smu_init(struct pp_hwmgr *hwmgr)
90 hwmgr->smu_backend = smu_data;
92 if (smu7_init(hwmgr)) {
100 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
111 result = smu7_upload_smu_firmware_image(hwmgr);
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
126 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
130 smu7_send_msg_to_smc_offset(hwmgr);
135 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
137 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
143 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
146 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
150 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
155 static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
160 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
167 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
171 result = smu7_upload_smu_firmware_image(hwmgr);
176 smu7_program_jump_on_start(hwmgr);
178 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
181 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
186 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
192 static int vegam_start_smu(struct pp_hwmgr *hwmgr)
195 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
198 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
199 smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
202 hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
206 result = vegam_start_smu_in_non_protection_mode(hwmgr);
208 result = vegam_start_smu_in_protection_mode(hwmgr);
215 smu7_read_smc_sram_dword(hwmgr,
220 result = smu7_request_smu_load_fw(hwmgr);
225 static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
227 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
228 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
233 result = smu7_read_smc_sram_dword(hwmgr,
243 result = smu7_read_smc_sram_dword(hwmgr,
255 result = smu7_read_smc_sram_dword(hwmgr,
263 result = smu7_read_smc_sram_dword(hwmgr,
273 result = smu7_read_smc_sram_dword(hwmgr,
283 result = smu7_read_smc_sram_dword(hwmgr,
289 hwmgr->microcode_version_info.SMC = tmp;
296 static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
298 return 1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
330 static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
332 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
335 (struct phm_ppt_v1_information *)(hwmgr->pptable);
345 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
349 cgs_write_ind_register(hwmgr->device,
352 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
354 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
356 smum_send_msg_to_smc_with_parameter(hwmgr,
363 static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
368 (struct phm_ppt_v1_information *)(hwmgr->pptable);
370 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
381 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
385 cgs_write_ind_register(hwmgr->device,
388 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
389 smum_send_msg_to_smc_with_parameter(hwmgr,
396 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
398 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
400 (struct phm_ppt_v1_information *)(hwmgr->pptable);
413 static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
417 vegam_update_uvd_smc_table(hwmgr);
420 vegam_update_vce_smc_table(hwmgr);
423 vegam_update_bif_smc_table(hwmgr);
431 static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
433 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
435 (struct phm_ppt_v1_information *)(hwmgr->pptable);
448 static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
451 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
475 static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
500 static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
507 (struct phm_ppt_v1_information *)(hwmgr->pptable);
529 static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
532 vegam_populate_smc_vddci_table(hwmgr, table);
533 vegam_populate_smc_mvdd_table(hwmgr, table);
534 vegam_populate_cac_table(hwmgr, table);
539 static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
542 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
544 (struct phm_ppt_v1_information *)(hwmgr->pptable);
562 static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
565 return vegam_populate_ulv_level(hwmgr, &table->Ulv);
568 static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
571 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
573 (struct vegam_smumgr *)(hwmgr->smu_backend);
593 /* To Do move to hwmgr */
600 static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
606 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
669 static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
672 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
677 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
679 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
719 static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
722 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
749 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
809 static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
815 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
817 (struct phm_ppt_v1_information *)(hwmgr->pptable);
820 result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
823 result = vegam_get_dependency_volt_by_clk(hwmgr,
839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
841 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
843 hwmgr->display_config->min_core_set_clock_in_sr);
864 static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
866 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
867 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
870 (struct phm_ppt_v1_information *)(hwmgr->pptable);
886 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
890 result = vegam_populate_single_graphic_level(hwmgr,
904 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
957 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
963 static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
968 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
981 static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
984 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
986 (struct phm_ppt_v1_information *)(hwmgr->pptable);
992 result = vegam_get_dependency_volt_by_clk(hwmgr,
1000 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1018 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1034 static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1036 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1037 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1053 result = vegam_populate_single_memory_level(hwmgr,
1079 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1085 static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1088 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1090 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1110 static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1115 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1117 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1126 result = vegam_get_dependency_volt_by_clk(hwmgr,
1135 result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1164 result = vegam_get_dependency_volt_by_clk(hwmgr,
1173 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1194 static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1201 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1204 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1230 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1244 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1256 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1262 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1263 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1264 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1265 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1266 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1277 static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1279 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1280 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1289 result = vegam_populate_memory_timing_parameters(hwmgr,
1299 hwmgr,
1307 static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1314 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1317 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1342 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1349 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1364 static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1368 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1401 static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1403 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1404 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1406 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1438 static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1440 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1445 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1448 &hwmgr->thermal_controller.advanceFanControlParameters;
1486 static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1490 (struct vegam_smumgr *)(hwmgr->smu_backend);
1494 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1500 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1533 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1540 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1542 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1547 static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1551 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1561 static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1563 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1564 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1574 (struct phm_ppt_v1_information *)hwmgr->pptable;
1578 if (!hwmgr->avfs_supported)
1581 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1636 result = smu7_read_smc_sram_dword(hwmgr,
1640 smu7_copy_bytes_to_smc(hwmgr,
1646 result = smu7_read_smc_sram_dword(hwmgr,
1650 smu7_copy_bytes_to_smc(hwmgr,
1667 static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1670 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1672 (struct vegam_smumgr *)(hwmgr->smu_backend);
1703 cgs_write_ind_register(hwmgr->device,
1717 cgs_write_ind_register(hwmgr->device,
1730 static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1732 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1743 static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1746 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1748 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1761 static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1763 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1767 if (smu7_read_smc_sram_dword(hwmgr,
1785 static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1788 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1797 static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1799 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1801 /* TO DO move to hwmgr */
1802 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1803 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1804 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1805 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1808 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1812 static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1815 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1824 static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1826 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1828 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1844 static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1846 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1849 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1851 if (smu7_read_smc_sram_dword(hwmgr,
1859 if (vegam_populate_svi_load_line(hwmgr))
1864 if (vegam_populate_tdc_limit(hwmgr))
1868 if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1874 if (0 != vegam_populate_temperature_scaler(hwmgr))
1879 if (vegam_populate_fuzzy_fan(hwmgr))
1884 if (vegam_populate_gnb_lpml(hwmgr))
1889 if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1894 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1905 static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1907 struct amdgpu_device *adev = hwmgr->adev;
1909 smum_send_msg_to_smc_with_parameter(hwmgr,
1917 static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
1920 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1921 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1924 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1932 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1935 vegam_initialize_power_tune_defaults(hwmgr);
1938 vegam_populate_smc_voltage_tables(hwmgr, table);
1941 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1945 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1953 result = vegam_populate_ulv_state(hwmgr, table);
1956 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1960 result = vegam_populate_smc_link_level(hwmgr, table);
1964 result = vegam_populate_all_graphic_levels(hwmgr);
1968 result = vegam_populate_all_memory_levels(hwmgr);
1972 result = vegam_populate_smc_acpi_level(hwmgr, table);
1976 result = vegam_populate_smc_vce_level(hwmgr, table);
1984 result = vegam_program_memory_timing_parameters(hwmgr);
1988 result = vegam_populate_smc_uvd_level(hwmgr, table);
1992 result = vegam_populate_smc_boot_level(hwmgr, table);
1996 result = vegam_populate_smc_initial_state(hwmgr);
2000 result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2006 result = vegam_populate_clock_stretcher_data_table(hwmgr);
2012 result = vegam_populate_avfs_parameters(hwmgr);
2042 result = vegam_populate_vr_config(hwmgr, table);
2049 if (atomctrl_get_pp_assign_pin(hwmgr,
2057 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2061 if (atomctrl_get_pp_assign_pin(hwmgr,
2064 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2066 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2067 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2071 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2076 if (atomctrl_get_pp_assign_pin(hwmgr,
2086 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2091 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2093 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2104 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2133 result = smu7_copy_bytes_to_smc(hwmgr,
2142 result = vegam_populate_pm_fuses(hwmgr);
2146 result = vegam_enable_reconfig_cus(hwmgr);
2199 static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2201 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2207 return vegam_program_memory_timing_parameters(hwmgr);
2212 static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2214 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2216 (struct vegam_smumgr *)(hwmgr->smu_backend);
2220 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2229 hwmgr,
2240 result = vegam_program_mem_timing_parameters(hwmgr);
2248 static int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2250 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2253 if (!hwmgr->avfs_supported)
2256 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2259 ret = smum_send_msg_to_smc(hwmgr,
2267 static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2269 PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2272 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,