Lines Matching defs:hwmgr
97 static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
102 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
105 result = smu7_upload_smu_firmware_image(hwmgr);
110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
114 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
129 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
135 smu7_send_msg_to_smc_offset(hwmgr);
138 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
142 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
149 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
155 static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
160 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
168 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
171 result = smu7_upload_smu_firmware_image(hwmgr);
177 smu7_program_jump_on_start(hwmgr);
180 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
184 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
188 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
194 static int tonga_start_smu(struct pp_hwmgr *hwmgr)
196 struct tonga_smumgr *priv = hwmgr->smu_backend;
200 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
202 if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
204 result = tonga_start_in_non_protection_mode(hwmgr);
208 result = tonga_start_in_protection_mode(hwmgr);
217 smu7_read_smc_sram_dword(hwmgr,
222 result = smu7_request_smu_load_fw(hwmgr);
227 static int tonga_smu_init(struct pp_hwmgr *hwmgr)
235 hwmgr->smu_backend = tonga_priv;
237 if (smu7_init(hwmgr)) {
246 static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
251 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
253 (struct phm_ppt_v1_information *)(hwmgr->pptable);
302 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
306 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
319 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
323 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
336 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
339 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
366 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
369 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
391 static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
396 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
398 (struct phm_ppt_v1_information *)(hwmgr->pptable);
446 static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
451 result = tonga_populate_smc_vddc_table(hwmgr, table);
456 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
461 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
466 result = tonga_populate_smc_mvdd_table(hwmgr, table);
471 result = tonga_populate_cac_tables(hwmgr, table);
479 static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
483 (struct phm_ppt_v1_information *)(hwmgr->pptable);
501 static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
504 return tonga_populate_ulv_level(hwmgr, &table->Ulv);
507 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
509 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
511 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
538 static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
541 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs);
560 reference_clock = atomctrl_get_reference_clock(hwmgr);
581 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
586 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
616 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
622 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
624 (struct phm_ppt_v1_information *)(hwmgr->pptable);
627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
629 if (hwmgr->od_enabled)
635 result = tonga_get_dependency_volt_by_clk(hwmgr,
659 hwmgr->display_config->min_core_set_clock_in_sr;
661 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
686 static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
688 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
689 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
690 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
711 result = tonga_populate_single_graphic_level(hwmgr,
780 result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
788 struct pp_hwmgr *hwmgr,
795 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
810 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
847 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
867 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
879 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
960 struct pp_hwmgr *hwmgr,
965 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
967 (struct phm_ppt_v1_information *)(hwmgr->pptable);
977 if (hwmgr->od_enabled)
983 result = tonga_get_dependency_volt_by_clk(hwmgr,
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1022 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1048 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
1049 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1051 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1060 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1063 result = tonga_calculate_mclk_params(hwmgr,
1086 static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1088 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1090 (struct tonga_smumgr *)(hwmgr->smu_backend);
1112 hwmgr,
1136 result = smu7_copy_bytes_to_smc(hwmgr,
1143 static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1146 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1148 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1173 static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1178 (struct tonga_smumgr *)(hwmgr->smu_backend);
1179 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1195 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1198 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1246 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
1307 static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1314 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1316 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1340 hwmgr,
1350 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1367 static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1374 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1376 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1399 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1413 static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1419 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1421 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1444 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1458 struct pp_hwmgr *hwmgr,
1469 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1475 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1476 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1477 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1486 static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1488 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1490 (struct tonga_smumgr *)(hwmgr->smu_backend);
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1511 hwmgr,
1522 static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1526 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1528 (struct tonga_smumgr *)(hwmgr->smu_backend);
1573 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1579 (struct tonga_smumgr *)(hwmgr->smu_backend);
1583 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1587 struct amdgpu_device *adev = hwmgr->adev;
1597 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1599 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1644 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1646 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1648 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1650 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1659 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1666 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1698 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1737 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1740 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1746 static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1749 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1797 static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
1799 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1812 result = smu7_read_smc_sram_dword(hwmgr,
1821 return smu7_write_smc_sram_dword(hwmgr,
1826 static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1829 (struct tonga_smumgr *)(hwmgr->smu_backend);
1833 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1873 static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1876 (struct tonga_smumgr *)(hwmgr->smu_backend);
1887 static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1891 (struct tonga_smumgr *)(hwmgr->smu_backend);
1894 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1909 static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1912 (struct tonga_smumgr *)(hwmgr->smu_backend);
1916 if (smu7_read_smc_sram_dword(hwmgr,
1930 static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1934 (struct tonga_smumgr *)(hwmgr->smu_backend);
1943 static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1945 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
1947 if ((hwmgr->thermal_controller.advanceFanControlParameters.
1949 (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
1950 hwmgr->thermal_controller.advanceFanControlParameters.
1951 usFanOutputSensitivity = hwmgr->thermal_controller.
1955 PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
1960 static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1964 (struct tonga_smumgr *)(hwmgr->smu_backend);
1973 static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1976 (struct tonga_smumgr *)(hwmgr->smu_backend);
1978 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1994 static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1997 (struct tonga_smumgr *)(hwmgr->smu_backend);
2000 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2002 if (smu7_read_smc_sram_dword(hwmgr,
2011 if (tonga_populate_svi_load_line(hwmgr))
2016 if (tonga_populate_tdc_limit(hwmgr))
2021 if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
2027 if (tonga_populate_temperature_scaler(hwmgr) != 0)
2033 if (tonga_populate_fuzzy_fan(hwmgr))
2040 if (tonga_populate_gnb_lpml(hwmgr))
2046 if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
2053 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
2063 static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
2066 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
2107 struct pp_hwmgr *hwmgr,
2112 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2132 static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2136 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2142 hwmgr,
2154 static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
2156 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2157 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2167 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
2177 hwmgr, address,
2184 static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2187 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2190 result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
2195 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
2200 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
2204 static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
2206 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2208 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2220 static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2223 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2225 (struct tonga_smumgr *)(hwmgr->smu_backend);
2228 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2236 tonga_initialize_power_tune_defaults(hwmgr);
2239 tonga_populate_smc_voltage_tables(hwmgr, table);
2241 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2246 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2253 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2259 result = tonga_populate_ulv_state(hwmgr, table);
2264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2268 result = tonga_populate_smc_link_level(hwmgr, table);
2272 result = tonga_populate_all_graphic_levels(hwmgr);
2276 result = tonga_populate_all_memory_levels(hwmgr);
2280 result = tonga_populate_smc_acpi_level(hwmgr, table);
2284 result = tonga_populate_smc_vce_level(hwmgr, table);
2288 result = tonga_populate_smc_acp_level(hwmgr, table);
2296 result = tonga_program_memory_timing_parameters(hwmgr);
2301 result = tonga_populate_smc_uvd_level(hwmgr, table);
2305 result = tonga_populate_smc_boot_level(hwmgr, table);
2309 tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
2313 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2315 result = tonga_populate_clock_stretcher_data_table(hwmgr);
2354 result = tonga_populate_vr_config(hwmgr, table);
2361 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
2364 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2368 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2372 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2375 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2379 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2383 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2387 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2389 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2393 if (atomctrl_get_pp_assign_pin(hwmgr,
2395 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2401 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2407 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2409 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2414 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2436 hwmgr,
2445 result = tonga_init_arb_table_index(hwmgr);
2449 tonga_populate_pm_fuses(hwmgr);
2453 result = tonga_populate_initial_mc_reg_table(hwmgr);
2460 static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2463 (struct tonga_smumgr *)(hwmgr->smu_backend);
2472 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2476 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2477 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2483 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2488 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
2493 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2498 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2502 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2503 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2504 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2505 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2507 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2508 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2509 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2510 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2515 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2516 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2517 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2524 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2532 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2534 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2538 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2542 res = smu7_copy_bytes_to_smc(hwmgr,
2552 static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2554 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2558 return tonga_program_memory_timing_parameters(hwmgr);
2563 static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2565 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2567 (struct tonga_smumgr *)(hwmgr->smu_backend);
2572 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2581 hwmgr,
2590 result = tonga_update_and_upload_mc_reg_table(hwmgr);
2596 result = tonga_program_mem_timing_parameters(hwmgr);
2675 static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2678 (struct tonga_smumgr *)(hwmgr->smu_backend);
2681 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2691 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2695 cgs_write_ind_register(hwmgr->device,
2699 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2701 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2703 smum_send_msg_to_smc_with_parameter(hwmgr,
2710 static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2713 (struct tonga_smumgr *)(hwmgr->smu_backend);
2716 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2726 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2730 cgs_write_ind_register(hwmgr->device,
2733 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2735 smum_send_msg_to_smc_with_parameter(hwmgr,
2742 static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2746 tonga_update_uvd_smc_table(hwmgr);
2749 tonga_update_vce_smc_table(hwmgr);
2757 static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
2759 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2760 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
2766 result = smu7_read_smc_sram_dword(hwmgr,
2776 result = smu7_read_smc_sram_dword(hwmgr,
2789 result = smu7_read_smc_sram_dword(hwmgr,
2797 result = smu7_read_smc_sram_dword(hwmgr,
2807 result = smu7_read_smc_sram_dword(hwmgr,
2817 result = smu7_read_smc_sram_dword(hwmgr,
2823 hwmgr->microcode_version_info.SMC = tmp;
2832 static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2834 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2974 static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2979 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2988 temp_reg = cgs_read_register(hwmgr->device,
3001 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3028 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3067 static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3070 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
3073 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
3081 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
3082 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
3083 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
3084 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
3085 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
3086 cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
3087 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
3088 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
3089 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
3090 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
3091 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
3092 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
3093 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
3094 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
3095 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
3096 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
3097 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
3098 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
3099 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
3100 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
3101 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
3102 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
3103 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
3104 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
3105 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
3106 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
3107 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
3108 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
3109 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
3110 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
3111 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
3112 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
3113 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
3114 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
3115 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
3116 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
3117 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
3118 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
3119 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
3120 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
3122 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
3129 result = tonga_set_mc_special_registers(hwmgr, ni_table);
3140 static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
3142 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
3147 static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr,
3150 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3152 (hwmgr->smu_backend);
3173 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
3182 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3184 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3196 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3199 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3203 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
3208 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
3217 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3219 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3231 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3234 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
3238 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);