powerplay/inc/smu9_driver_if.h

84   uint8_t  SsOn;
85   uint8_t  Did;      /* DID */
93   uint8_t a0_shift;
94   uint8_t a1_shift;
95   uint8_t a2_shift;
96   uint8_t padding;
104   uint8_t m1_shift;
105   uint8_t m2_shift;
106   uint8_t b_shift;
107   uint8_t padding;
143   uint8_t  Liquid1_I2C_address;
144   uint8_t  Liquid2_I2C_address;
145   uint8_t  Vr_I2C_address;
146   uint8_t  Plx_I2C_address;
148   uint8_t  GeminiMode;
149   uint8_t  spare17[3];
153   uint8_t  Liquid_I2C_LineSCL;
154   uint8_t  Liquid_I2C_LineSDA;
155   uint8_t  Vr_I2C_LineSCL;
156   uint8_t  Vr_I2C_LineSDA;
157   uint8_t  Plx_I2C_LineSCL;
158   uint8_t  Plx_I2C_LineSDA;
159   uint8_t  paddingx[2];
162   uint8_t  UlvOffsetVid;     /* SVI2 VID */
163   uint8_t  UlvSmnclkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
164   uint8_t  UlvMp1clkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
165   uint8_t  UlvGfxclkBypass;  /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
168   uint8_t      SocVid[NUM_EVV_VOLTAGE_LEVELS];
171   uint8_t      MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
172   uint8_t      MaxVoltageVid; /* Maximum Voltage allowable */
173   uint8_t      MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
174   uint8_t      padding8;
176   uint8_t      UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
177   uint8_t      UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
178   uint8_t      padding8_2[2];
183   uint8_t      SocclkDid[NUM_SOCCLK_DPM_LEVELS];          /* DID */
184   uint8_t      SocDpmVoltageIndex[NUM_SOCCLK_DPM_LEVELS];
186   uint8_t      VclkDid[NUM_UVD_DPM_LEVELS];            /* DID */
187   uint8_t      DclkDid[NUM_UVD_DPM_LEVELS];            /* DID */
188   uint8_t      UvdDpmVoltageIndex[NUM_UVD_DPM_LEVELS];
190   uint8_t      EclkDid[NUM_VCE_DPM_LEVELS];            /* DID */
191   uint8_t      VceDpmVoltageIndex[NUM_VCE_DPM_LEVELS];
193   uint8_t      Mp0clkDid[NUM_MP0CLK_DPM_LEVELS];          /* DID */
194   uint8_t      Mp0DpmVoltageIndex[NUM_MP0CLK_DPM_LEVELS];
199   uint8_t      GfxDpmVoltageMode;
200   uint8_t      SocDpmVoltageMode;
201   uint8_t      UclkDpmVoltageMode;
202   uint8_t      UvdDpmVoltageMode;
204   uint8_t      VceDpmVoltageMode;
205   uint8_t      Mp0DpmVoltageMode;
206   uint8_t      DisplayDpmVoltageMode;
207   uint8_t      padding8_3;
215   uint8_t      GfxclkAverageAlpha;
216   uint8_t      SocclkAverageAlpha;
217   uint8_t      UclkAverageAlpha;
218   uint8_t      GfxActivityAverageAlpha;
221   uint8_t      MemVid[NUM_UCLK_DPM_LEVELS];    /* VID */
223   uint8_t      MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
224   uint8_t      LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
225   uint8_t      paddingUclk[3];
230   uint8_t      CksEnable[NUM_GFXCLK_DPM_LEVELS];
231   uint8_t      CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
234   uint8_t      PspLevelMap[NUM_PSP_LEVEL_MAP];
237   uint8_t     PcieGenSpeed[NUM_LINK_LEVELS];           /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
238   uint8_t     PcieLaneCount[NUM_LINK_LEVELS];          /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
239   uint8_t     LclkDid[NUM_LINK_LEVELS];                /* Leave at 0 to use hardcoded values in FW */
240   uint8_t     paddingLinkDpm[2];
259   uint8_t      FanZeroRpmEnable;
260   uint8_t      FanSpare;
269   uint8_t      AcDcGpio;        /* GPIO pin configured for AC/DC switching */
270   uint8_t      AcDcPolarity;    /* GPIO polarity for AC/DC switching */
271   uint8_t      VR0HotGpio;      /* GPIO pin configured for VR0 HOT event */
272   uint8_t      VR0HotPolarity;  /* GPIO polarity for VR0 HOT event */
273   uint8_t      VR1HotGpio;      /* GPIO pin configured for VR1 HOT event */
274   uint8_t      VR1HotPolarity;  /* GPIO polarity for VR1 HOT event */
275   uint8_t      Padding1;       /* replace GPIO pin configured for CTF */
276   uint8_t      Padding2;       /* replace GPIO polarity for CTF */
279   uint8_t      LedPin0;         /* GPIO number for LedPin[0] */
280   uint8_t      LedPin1;         /* GPIO number for LedPin[1] */
281   uint8_t      LedPin2;         /* GPIO number for LedPin[2] */
282   uint8_t      padding8_4;
285   uint8_t      OverrideBtcGbCksOn;
286   uint8_t      OverrideAvfsGbCksOn;
287   uint8_t      PaddingAvfs8[2];
295   uint8_t      StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
306   uint8_t      EnableBoostState;
307   uint8_t      AConstant_Shift;
308   uint8_t      DC_tol_sigma_Shift;
309   uint8_t      PSM_Age_CompFactor_Shift;
316   uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];
335   uint8_t  WmSetting;
336   uint8_t  Padding[3];
386   uint8_t  AvfsEn;
387   uint8_t  AvfsVersion;
388   uint8_t  Padding[2];