Lines Matching refs:uint8_t
43 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
44 uint8_t postdiv; /* divide by 2^n */
53 uint8_t Smio;
54 uint8_t padding;
70 uint8_t PllRange;
71 uint8_t SSc_En;
84 uint8_t pcieDpmLevel;
85 uint8_t DeepSleepDivId;
93 uint8_t SclkDid;
94 uint8_t padding;
95 uint8_t EnabledForActivity;
96 uint8_t EnabledForThrottle;
97 uint8_t UpHyst;
98 uint8_t DownHyst;
99 uint8_t VoltageDownHyst;
100 uint8_t PowerThrottle;
104 uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
114 uint8_t SclkDid;
115 uint8_t DisplayWatermark;
116 uint8_t DeepSleepDivId;
117 uint8_t padding;
130 uint8_t VddcOffsetVid;
131 uint8_t VddcPhase;
144 uint8_t StutterEnable;
145 uint8_t EnabledForThrottle;
146 uint8_t EnabledForActivity;
147 uint8_t padding_0;
149 uint8_t UpHyst;
150 uint8_t DownHyst;
151 uint8_t VoltageDownHyst;
152 uint8_t padding_1;
155 uint8_t DisplayWatermark;
156 uint8_t padding_2;
160 uint8_t Postdiv;
161 uint8_t padding_3[3];
167 uint8_t PcieGenSpeed;
168 uint8_t PcieLaneCount;
169 uint8_t EnabledForActivity;
170 uint8_t SPC;
202 uint8_t VclkDivider;
203 uint8_t DclkDivider;
204 uint8_t padding[2];
213 uint8_t Divider;
214 uint8_t padding[3];
229 uint8_t DisplayWatermark;
230 uint8_t McArbIndex;
231 uint8_t McRegIndex;
232 uint8_t SeqIndex;
233 uint8_t SclkDid;
236 uint8_t PCIeGen;
256 uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC];
257 uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC];
258 uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC];
260 uint8_t GraphicsDpmLevelCount;
261 uint8_t MemoryDpmLevelCount;
262 uint8_t LinkLevelCount;
263 uint8_t MasterDeepSleepControl;
265 uint8_t UvdLevelCount;
266 uint8_t VceLevelCount;
267 uint8_t AcpLevelCount;
268 uint8_t SamuLevelCount;
270 uint8_t ThermOutGpio;
271 uint8_t ThermOutPolarity;
272 uint8_t ThermOutMode;
273 uint8_t BootPhases;
275 uint8_t VRHotLevel;
276 uint8_t LdoRefSel;
278 uint8_t Reserved1[2];
298 uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];
303 uint8_t UvdBootLevel;
304 uint8_t VceBootLevel;
305 uint8_t AcpBootLevel;
306 uint8_t SamuBootLevel;
308 uint8_t GraphicsBootLevel;
309 uint8_t GraphicsVoltageChangeEnable;
310 uint8_t GraphicsThermThrottleEnable;
311 uint8_t GraphicsInterval;
313 uint8_t VoltageInterval;
314 uint8_t ThermalInterval;
318 uint8_t MemoryBootLevel;
319 uint8_t MemoryVoltageChangeEnable;
322 uint8_t MemoryInterval;
323 uint8_t MemoryThermThrottleEnable;
328 uint8_t PCIeBootLinkLevel;
329 uint8_t PCIeGenInterval;
330 uint8_t DTEInterval;
331 uint8_t DTEMode;
333 uint8_t SVI2Enable;
334 uint8_t VRHotGpio;
335 uint8_t AcDcGpio;
336 uint8_t ThermGpio;
362 uint8_t ClockStretcherAmount;
363 uint8_t Sclk_CKS_masterEn0_7;
364 uint8_t Sclk_CKS_masterEn8_15;
365 uint8_t DPMFreezeAndForced;
367 uint8_t Sclk_voltageOffset[8];
398 uint8_t TempSrc;
422 uint8_t TdpClampMode;
423 uint8_t TdcClampMode;
424 uint8_t ThermClampMode;
425 uint8_t VoltageBusy;
429 uint8_t LevelChangeInProgress;
430 uint8_t UpHyst;
432 uint8_t DownHyst;
433 uint8_t VoltageDownHyst;
434 uint8_t DpmEnable;
435 uint8_t DpmRunning;
437 uint8_t DpmForce;
438 uint8_t DpmForceLevel;
439 uint8_t padding2;
440 uint8_t McArbIndex;
444 uint8_t AcpiReq;
445 uint8_t AcpiAck;
446 uint8_t MclkSwitchInProgress;
447 uint8_t MclkSwitchCritical;
449 uint8_t IgnoreVBlank;
450 uint8_t TargetMclkIndex;
451 uint8_t TargetMvddIndex;
452 uint8_t MclkSwitchResult;
455 uint8_t VbiWaitCounter;
456 uint8_t EnabledLevelsChange;
461 void (*TargetStateCalculator)(uint8_t);
462 void (*SavedTargetStateCalculator)(uint8_t);
470 uint8_t fastSwitch;
471 uint8_t Save_PIC_VDDGFX_EXIT;
472 uint8_t Save_PIC_VDDGFX_ENTER;
473 uint8_t VbiTimeout;
481 uint8_t EnterUlv;
482 uint8_t ExitUlv;
483 uint8_t UlvActive;
484 uint8_t WaitingForUlv;
485 uint8_t UlvEnable;
486 uint8_t UlvRunning;
487 uint8_t UlvMasterEnable;
488 uint8_t padding;
507 uint8_t VddGfxEnable;
508 uint8_t VddGfxActive;
509 uint8_t VPUResetOccured;
510 uint8_t padding;
523 uint8_t Enable;
524 uint8_t Running;
535 uint8_t Enable;
536 uint8_t Running;
542 uint8_t PowerSharingEnabled;
543 uint8_t PowerSharingCounter;
544 uint8_t PowerSharingINTEnabled;
545 uint8_t GFXActivityCounterEnabled;
548 uint8_t RollOverRequired;
549 uint8_t RollOverCount;
550 uint8_t padding[2];
570 uint8_t VariantID;
571 uint8_t spare997;
585 uint8_t LastACPIRequest;
586 uint8_t CgBifResp;
587 uint8_t RequestType;
588 uint8_t Padding;
595 uint8_t BapmVddCVidHiSidd[8];
597 uint8_t BapmVddCVidLoSidd[8];
599 uint8_t VddCVid[8];
601 uint8_t SviLoadLineEn;
602 uint8_t SviLoadLineVddC;
603 uint8_t SviLoadLineTrimVddC;
604 uint8_t SviLoadLineOffsetVddC;
607 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
608 uint8_t TDC_MAWt;
610 uint8_t TdcWaterfallCtl;
611 uint8_t LPMLTemperatureMin;
612 uint8_t LPMLTemperatureMax;
613 uint8_t Reserved;
615 uint8_t LPMLTemperatureScaler[16];
622 uint8_t GnbLPML[16];
624 uint8_t GnbLPMLMaxVid;
625 uint8_t GnbLPMLMinVid;
626 uint8_t Reserved1[2];
632 uint8_t Version;
633 uint8_t padding;
661 uint8_t type;
662 uint8_t mode;
663 uint8_t filler_0[2];
670 uint8_t Enabled;
671 uint8_t Type;
672 uint8_t padding[2];
774 uint8_t Enabled;
775 uint8_t WaterfallUp;
776 uint8_t WaterfallDown;
777 uint8_t WaterfallLimit;
778 uint8_t CurrMaxCu;
779 uint8_t TargMaxCu;
780 uint8_t ClampMode;
781 uint8_t Active;
782 uint8_t MaxSupportedCu;
783 uint8_t MinSupportedCu;
784 uint8_t PendingGfxCuHostInterrupt;
785 uint8_t LastFilteredMaxCuInteger;
790 uint8_t ForceCu;
791 uint8_t ForceCuCount;
792 uint8_t AcModeMaxCu;
793 uint8_t DcModeMaxCu;