Lines Matching refs:uint8_t
44 uint8_t vco_setting;
45 uint8_t postdiv;
55 uint8_t Smio;
56 uint8_t padding;
72 uint8_t PllRange;
73 uint8_t SSc_En;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
92 uint8_t SclkDid;
93 uint8_t padding;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
96 uint8_t UpHyst;
97 uint8_t DownHyst;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
109 uint8_t SclkDid;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
112 uint8_t padding;
125 uint8_t VddcOffsetVid;
126 uint8_t VddcPhase;
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
142 uint8_t padding_0;
144 uint8_t UpHyst;
145 uint8_t DownHyst;
146 uint8_t VoltageDownHyst;
147 uint8_t padding_1;
150 uint8_t DisplayWatermark;
151 uint8_t Reserved;
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
160 uint8_t SPC;
172 uint8_t McArbBurstTime;
173 uint8_t padding[3];
188 uint8_t VclkDivider;
189 uint8_t DclkDivider;
190 uint8_t padding[2];
198 uint8_t Divider;
199 uint8_t padding[3];
214 uint8_t DisplayWatermark;
215 uint8_t McArbIndex;
216 uint8_t McRegIndex;
217 uint8_t SeqIndex;
218 uint8_t SclkDid;
221 uint8_t PCIeGen;
231 uint8_t m1_shift;
232 uint8_t m2_shift;
253 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
254 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
255 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
257 uint8_t GraphicsDpmLevelCount;
258 uint8_t MemoryDpmLevelCount;
259 uint8_t LinkLevelCount;
260 uint8_t MasterDeepSleepControl;
262 uint8_t UvdLevelCount;
263 uint8_t VceLevelCount;
264 uint8_t AcpLevelCount;
265 uint8_t SamuLevelCount;
267 uint8_t ThermOutGpio;
268 uint8_t ThermOutPolarity;
269 uint8_t ThermOutMode;
270 uint8_t BootPhases;
272 uint8_t VRHotLevel;
273 uint8_t LdoRefSel;
274 uint8_t SharedRails;
275 uint8_t Reserved1;
293 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
298 uint8_t UvdBootLevel;
299 uint8_t VceBootLevel;
300 uint8_t AcpBootLevel;
301 uint8_t SamuBootLevel;
303 uint8_t GraphicsBootLevel;
304 uint8_t GraphicsVoltageChangeEnable;
305 uint8_t GraphicsThermThrottleEnable;
306 uint8_t GraphicsInterval;
308 uint8_t VoltageInterval;
309 uint8_t ThermalInterval;
313 uint8_t MemoryBootLevel;
314 uint8_t MemoryVoltageChangeEnable;
317 uint8_t MemoryInterval;
318 uint8_t MemoryThermThrottleEnable;
323 uint8_t PCIeBootLinkLevel;
324 uint8_t PCIeGenInterval;
325 uint8_t DTEInterval;
326 uint8_t DTEMode;
328 uint8_t SVI2Enable;
329 uint8_t VRHotGpio;
330 uint8_t AcDcGpio;
331 uint8_t ThermGpio;
357 uint8_t ClockStretcherAmount;
358 uint8_t Sclk_CKS_masterEn0_7;
359 uint8_t Sclk_CKS_masterEn8_15;
360 uint8_t DPMFreezeAndForced;
362 uint8_t Sclk_voltageOffset[8];
393 uint8_t TempSrc;
416 uint8_t TdpClampMode;
417 uint8_t TdcClampMode;
418 uint8_t ThermClampMode;
419 uint8_t VoltageBusy;
423 uint8_t LevelChangeInProgress;
424 uint8_t UpHyst;
426 uint8_t DownHyst;
427 uint8_t VoltageDownHyst;
428 uint8_t DpmEnable;
429 uint8_t DpmRunning;
431 uint8_t DpmForce;
432 uint8_t DpmForceLevel;
433 uint8_t padding2;
434 uint8_t McArbIndex;
438 uint8_t AcpiReq;
439 uint8_t AcpiAck;
440 uint8_t MclkSwitchInProgress;
441 uint8_t MclkSwitchCritical;
443 uint8_t IgnoreVBlank;
444 uint8_t TargetMclkIndex;
446 uint8_t VbiWaitCounter;
447 uint8_t EnabledLevelsChange;
452 void (*TargetStateCalculator)(uint8_t);
453 void (*SavedTargetStateCalculator)(uint8_t);
461 uint8_t fastSwitch;
462 uint8_t Save_PIC_VDDGFX_EXIT;
463 uint8_t Save_PIC_VDDGFX_ENTER;
464 uint8_t padding;
470 uint8_t EnterUlv;
471 uint8_t ExitUlv;
472 uint8_t UlvActive;
473 uint8_t WaitingForUlv;
474 uint8_t UlvEnable;
475 uint8_t UlvRunning;
476 uint8_t UlvMasterEnable;
477 uint8_t padding;
496 uint8_t VddGfxEnable;
497 uint8_t VddGfxActive;
498 uint8_t VPUResetOccured;
499 uint8_t padding;
512 uint8_t Enable;
513 uint8_t Running;
524 uint8_t Enable;
525 uint8_t Running;
550 uint8_t VariantID;
551 uint8_t spare997;
565 uint8_t LastACPIRequest;
566 uint8_t CgBifResp;
567 uint8_t RequestType;
568 uint8_t Padding;
575 uint8_t BapmVddCVidHiSidd[8];
576 uint8_t BapmVddCVidLoSidd[8];
577 uint8_t VddCVid[8];
578 uint8_t SviLoadLineEn;
579 uint8_t SviLoadLineVddC;
580 uint8_t SviLoadLineTrimVddC;
581 uint8_t SviLoadLineOffsetVddC;
583 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
584 uint8_t TDC_MAWt;
585 uint8_t TdcWaterfallCtl;
586 uint8_t LPMLTemperatureMin;
587 uint8_t LPMLTemperatureMax;
588 uint8_t Reserved;
590 uint8_t LPMLTemperatureScaler[16];
597 uint8_t GnbLPML[16];
599 uint8_t GnbLPMLMaxVid;
600 uint8_t GnbLPMLMinVid;
601 uint8_t Reserved1[2];
633 uint8_t type;
634 uint8_t mode;
635 uint8_t filler_0[2];
642 uint8_t Enabled;
643 uint8_t Type;
644 uint8_t padding[2];
739 uint8_t Enabled;
740 uint8_t WaterfallUp;
741 uint8_t WaterfallDown;
742 uint8_t WaterfallLimit;
743 uint8_t CurrMaxCu;
744 uint8_t TargMaxCu;
745 uint8_t ClampMode;
746 uint8_t Active;
747 uint8_t MaxSupportedCu;
748 uint8_t MinSupportedCu;
749 uint8_t PendingGfxCuHostInterrupt;
750 uint8_t LastFilteredMaxCuInteger;
755 uint8_t ForceCu;
756 uint8_t ForceCuCount;
757 uint8_t spare[2];