Lines Matching refs:uint8_t
32 uint8_t Smio;
33 uint8_t padding;
49 uint8_t pcieDpmLevel;
50 uint8_t DeepSleepDivId;
58 uint8_t SclkDid;
59 uint8_t DisplayWatermark;
60 uint8_t EnabledForActivity;
61 uint8_t EnabledForThrottle;
62 uint8_t UpHyst;
63 uint8_t DownHyst;
64 uint8_t VoltageDownHyst;
65 uint8_t PowerThrottle;
74 uint8_t SclkDid;
75 uint8_t DisplayWatermark;
76 uint8_t DeepSleepDivId;
77 uint8_t padding;
94 uint8_t VddcOffsetVid;
95 uint8_t VddcPhase;
107 uint8_t StutterEnable;
108 uint8_t FreqRange;
109 uint8_t EnabledForThrottle;
110 uint8_t EnabledForActivity;
112 uint8_t UpHyst;
113 uint8_t DownHyst;
114 uint8_t VoltageDownHyst;
115 uint8_t padding;
118 uint8_t DisplayWatermark;
119 uint8_t MclkDivider;
125 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
126 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
127 uint8_t EnabledForActivity;
128 uint8_t SPC;
141 uint8_t McArbBurstTime;
142 uint8_t TRRDS;
143 uint8_t TRRDL;
144 uint8_t padding;
160 uint8_t VclkDivider;
161 uint8_t DclkDivider;
162 uint8_t padding[2];
171 uint8_t Divider;
172 uint8_t padding[3];
187 uint8_t DisplayWatermark;
188 uint8_t McArbIndex;
189 uint8_t McRegIndex;
190 uint8_t SeqIndex;
191 uint8_t SclkDid;
194 uint8_t PCIeGen;
218 uint8_t BapmVddcVidHiSidd[SMU73_MAX_LEVELS_VDDC];
219 uint8_t BapmVddcVidLoSidd[SMU73_MAX_LEVELS_VDDC];
220 uint8_t BapmVddcVidHiSidd2[SMU73_MAX_LEVELS_VDDC];
222 uint8_t GraphicsDpmLevelCount;
223 uint8_t MemoryDpmLevelCount;
224 uint8_t LinkLevelCount;
225 uint8_t MasterDeepSleepControl;
227 uint8_t UvdLevelCount;
228 uint8_t VceLevelCount;
229 uint8_t AcpLevelCount;
230 uint8_t SamuLevelCount;
232 uint8_t ThermOutGpio;
233 uint8_t ThermOutPolarity;
234 uint8_t ThermOutMode;
235 uint8_t BootPhases;
253 uint8_t UvdBootLevel;
254 uint8_t VceBootLevel;
255 uint8_t AcpBootLevel;
256 uint8_t SamuBootLevel;
258 uint8_t GraphicsBootLevel;
259 uint8_t GraphicsVoltageChangeEnable;
260 uint8_t GraphicsThermThrottleEnable;
261 uint8_t GraphicsInterval;
263 uint8_t VoltageInterval;
264 uint8_t ThermalInterval;
268 uint8_t MemoryBootLevel;
269 uint8_t MemoryVoltageChangeEnable;
272 uint8_t MemoryInterval;
273 uint8_t MemoryThermThrottleEnable;
278 uint8_t PCIeBootLinkLevel;
279 uint8_t PCIeGenInterval;
280 uint8_t DTEInterval;
281 uint8_t DTEMode;
283 uint8_t SVI2Enable;
284 uint8_t VRHotGpio;
285 uint8_t AcDcGpio;
286 uint8_t ThermGpio;
313 uint8_t Liquid1_I2C_address;
314 uint8_t Liquid2_I2C_address;
315 uint8_t Vr_I2C_address;
316 uint8_t Plx_I2C_address;
318 uint8_t GeminiMode;
319 uint8_t spare17[3];
323 uint8_t Liquid_I2C_LineSCL;
324 uint8_t Liquid_I2C_LineSDA;
325 uint8_t Vr_I2C_LineSCL;
326 uint8_t Vr_I2C_LineSDA;
327 uint8_t Plx_I2C_LineSCL;
328 uint8_t Plx_I2C_LineSDA;
330 uint8_t spare1253[2];
333 uint8_t DTEAmbientTempBase;
334 uint8_t DTETjOffset;
335 uint8_t GpuTjMax;
336 uint8_t GpuTjHyst;
346 uint8_t ClockStretcherAmount;
347 uint8_t Sclk_CKS_masterEn0_7;
348 uint8_t Sclk_CKS_masterEn8_15;
349 uint8_t DPMFreezeAndForced;
351 uint8_t Sclk_voltageOffset[8];
378 uint8_t TempSrc;
403 uint8_t TdpClampMode;
404 uint8_t TdcClampMode;
405 uint8_t ThermClampMode;
406 uint8_t VoltageBusy;
410 uint8_t LevelChangeInProgress;
411 uint8_t UpHyst;
413 uint8_t DownHyst;
414 uint8_t VoltageDownHyst;
415 uint8_t DpmEnable;
416 uint8_t DpmRunning;
418 uint8_t DpmForce;
419 uint8_t DpmForceLevel;
420 uint8_t DisplayWatermark;
421 uint8_t McArbIndex;
425 uint8_t AcpiReq;
426 uint8_t AcpiAck;
427 uint8_t MclkSwitchInProgress;
428 uint8_t MclkSwitchCritical;
430 uint8_t IgnoreVBlank;
431 uint8_t TargetMclkIndex;
432 uint8_t TargetMvddIndex;
433 uint8_t MclkSwitchResult;
436 uint8_t VbiWaitCounter;
437 uint8_t EnabledLevelsChange;
442 void (*TargetStateCalculator)(uint8_t);
443 void (*SavedTargetStateCalculator)(uint8_t);
451 uint8_t fastSwitch;
452 uint8_t Save_PIC_VDDGFX_EXIT;
453 uint8_t Save_PIC_VDDGFX_ENTER;
454 uint8_t padding;
461 uint8_t EnterUlv;
462 uint8_t ExitUlv;
463 uint8_t UlvActive;
464 uint8_t WaitingForUlv;
465 uint8_t UlvEnable;
466 uint8_t UlvRunning;
467 uint8_t UlvMasterEnable;
468 uint8_t padding;
487 uint8_t VddGfxEnable;
488 uint8_t VddGfxActive;
489 uint8_t VPUResetOccured;
490 uint8_t padding;
503 uint8_t Enable;
504 uint8_t Running;
515 uint8_t Enable;
516 uint8_t Running;
541 uint8_t VariantID;
542 uint8_t spare997;
556 uint8_t LastACPIRequest;
557 uint8_t CgBifResp;
558 uint8_t RequestType;
559 uint8_t Padding;
570 uint8_t m1_shift;
571 uint8_t m2_shift;
578 uint8_t BapmVddCVidHiSidd[8];
581 uint8_t BapmVddCVidLoSidd[8];
584 uint8_t VddCVid[8];
587 uint8_t SviLoadLineEn;
588 uint8_t SviLoadLineVddC;
589 uint8_t SviLoadLineTrimVddC;
590 uint8_t SviLoadLineOffsetVddC;
594 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
595 uint8_t TDC_MAWt;
598 uint8_t TdcWaterfallCtl;
599 uint8_t LPMLTemperatureMin;
600 uint8_t LPMLTemperatureMax;
601 uint8_t Reserved;
604 uint8_t LPMLTemperatureScaler[16];
613 uint8_t GnbLPML[16];
616 uint8_t GnbLPMLMaxVid;
617 uint8_t GnbLPMLMinVid;
618 uint8_t Reserved1[2];
652 uint8_t type;
653 uint8_t mode;
654 uint8_t filler_0[2];
661 uint8_t Enabled;
662 uint8_t Type;
663 uint8_t padding[2];