Lines Matching refs:uint8_t
41 uint8_t Smio;
42 uint8_t padding;
54 uint8_t pcieDpmLevel;
55 uint8_t DeepSleepDivId;
64 uint8_t SclkDid;
65 uint8_t DisplayWatermark;
66 uint8_t EnabledForActivity;
67 uint8_t EnabledForThrottle;
68 uint8_t UpHyst;
69 uint8_t DownHyst;
70 uint8_t VoltageDownHyst;
71 uint8_t PowerThrottle;
82 uint8_t SclkDid;
83 uint8_t DisplayWatermark;
84 uint8_t DeepSleepDivId;
85 uint8_t padding;
103 uint8_t VddcOffsetVid;
104 uint8_t VddcPhase;
119 uint8_t EdcReadEnable;
120 uint8_t EdcWriteEnable;
121 uint8_t RttEnable;
122 uint8_t StutterEnable;
124 uint8_t StrobeEnable;
125 uint8_t StrobeRatio;
126 uint8_t EnabledForThrottle;
127 uint8_t EnabledForActivity;
129 uint8_t UpHyst;
130 uint8_t DownHyst;
131 uint8_t VoltageDownHyst;
132 uint8_t padding;
135 uint8_t DisplayWatermark;
136 uint8_t padding1;
153 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
155 uint8_t EnabledForActivity;
156 uint8_t SPC;
171 uint8_t McArbBurstTime;
172 uint8_t padding[3];
191 uint8_t MinVddcPhases;
192 uint8_t VclkDivider;
193 uint8_t DclkDivider;
194 uint8_t padding[3];
204 uint8_t MinPhases;
205 uint8_t Divider;
225 uint8_t DisplayWatermark;
226 uint8_t McArbIndex;
227 uint8_t McRegIndex;
228 uint8_t SeqIndex;
229 uint8_t SclkDid;
232 uint8_t PCIeGen;
262 uint8_t GraphicsDpmLevelCount;
263 uint8_t MemoryDpmLevelCount;
264 uint8_t LinkLevelCount;
265 uint8_t MasterDeepSleepControl;
279 uint8_t GraphicsBootLevel;
280 uint8_t GraphicsVoltageChangeEnable;
281 uint8_t GraphicsThermThrottleEnable;
282 uint8_t GraphicsInterval;
284 uint8_t VoltageInterval;
285 uint8_t ThermalInterval;
289 uint8_t MemoryBootLevel;
290 uint8_t MemoryVoltageChangeEnable;
292 uint8_t MemoryInterval;
293 uint8_t MemoryThermThrottleEnable;
294 uint8_t MergedVddci;
295 uint8_t padding2;
300 uint8_t PCIeBootLinkLevel;
301 uint8_t PCIeGenInterval;
302 uint8_t DTEInterval;
303 uint8_t DTEMode;
305 uint8_t SVI2Enable;
306 uint8_t VRHotGpio;
307 uint8_t AcDcGpio;
308 uint8_t ThermGpio;
321 uint8_t DTEAmbientTempBase;
322 uint8_t DTETjOffset;
323 uint8_t GpuTjMax;
324 uint8_t GpuTjHyst;
367 uint8_t last;
368 uint8_t reserved[3];
395 uint8_t TempSrc;
419 uint8_t TdpClampMode;
420 uint8_t TdcClampMode;
421 uint8_t ThermClampMode;
422 uint8_t VoltageBusy;
426 uint8_t LevelChangeInProgress;
427 uint8_t UpHyst;
429 uint8_t DownHyst;
430 uint8_t VoltageDownHyst;
431 uint8_t DpmEnable;
432 uint8_t DpmRunning;
434 uint8_t DpmForce;
435 uint8_t DpmForceLevel;
436 uint8_t DisplayWatermark;
437 uint8_t McArbIndex;
441 uint8_t AcpiReq;
442 uint8_t AcpiAck;
443 uint8_t MclkSwitchInProgress;
444 uint8_t MclkSwitchCritical;
446 uint8_t TargetMclkIndex;
447 uint8_t TargetMvddIndex;
448 uint8_t MclkSwitchResult;
450 uint8_t EnabledLevelsChange;
455 void (*TargetStateCalculator)(uint8_t);
456 void (*SavedTargetStateCalculator)(uint8_t);
462 uint8_t padding[2];
469 uint8_t EnterUlv;
470 uint8_t ExitUlv;
471 uint8_t UlvActive;
472 uint8_t WaitingForUlv;
473 uint8_t UlvEnable;
474 uint8_t UlvRunning;
475 uint8_t UlvMasterEnable;
476 uint8_t padding;
485 uint8_t VddGfxEnable;
486 uint8_t VddGfxActive;
487 uint8_t padding[2];
497 uint8_t LastACPIRequest;
498 uint8_t CgBifResp;
499 uint8_t RequestType;
500 uint8_t Padding;
509 uint8_t BapmVddCVidHiSidd[8];
512 uint8_t BapmVddCVidLoSidd[8];
515 uint8_t VddCVid[8];
518 uint8_t SviLoadLineEn;
519 uint8_t SviLoadLineVddC;
520 uint8_t SviLoadLineTrimVddC;
521 uint8_t SviLoadLineOffsetVddC;
525 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
526 uint8_t TDC_MAWt;
529 uint8_t TdcWaterfallCtl;
530 uint8_t LPMLTemperatureMin;
531 uint8_t LPMLTemperatureMax;
532 uint8_t Reserved;
535 uint8_t LPMLTemperatureScaler[16];
544 uint8_t GnbLPML[16];
547 uint8_t GnbLPMLMaxVid;
548 uint8_t GnbLPMLMinVid;
549 uint8_t Reserved1[2];
565 uint8_t type;
566 uint8_t mode;
567 uint8_t filler_0[2];
574 uint8_t Enabled;
575 uint8_t Type;
576 uint8_t padding[2];