powerplay/hwmgr/vega10_processpptables.c

59 		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
875 	int result = 0;
935 		result = get_mm_clock_voltage_table(hwmgr,
939 	if (!result && powerplay_table->usPowerTuneTableOffset)
940 		result = get_tdp_table(hwmgr,
944 	if (!result && powerplay_table->usSocclkDependencyTableOffset)
945 		result = get_socclk_voltage_dependency_table(hwmgr,
949 	if (!result && powerplay_table->usGfxclkDependencyTableOffset)
950 		result = get_gfxclk_voltage_dependency_table(hwmgr,
954 	if (!result && powerplay_table->usPixclkDependencyTableOffset)
955 		result = get_pix_clk_voltage_dependency_table(hwmgr,
960 	if (!result && powerplay_table->usPhyClkDependencyTableOffset)
961 		result = get_pix_clk_voltage_dependency_table(hwmgr,
966 	if (!result && powerplay_table->usDispClkDependencyTableOffset)
967 		result = get_pix_clk_voltage_dependency_table(hwmgr,
972 	if (!result && powerplay_table->usDcefclkDependencyTableOffset)
973 		result = get_dcefclk_voltage_dependency_table(hwmgr,
977 	if (!result && powerplay_table->usMclkDependencyTableOffset)
978 		result = get_mclk_voltage_dependency_table(hwmgr,
982 	if (!result && powerplay_table->usPCIETableOffset)
983 		result = get_pcie_table(hwmgr,
987 	if (!result && powerplay_table->usHardLimitTableOffset)
988 		result = get_hard_limits(hwmgr,
1001 	if (!result &&
1004 		result = get_valid_clk(hwmgr,
1008 	if (!result &&
1011 		result = get_valid_clk(hwmgr,
1015 	if (!result &&
1018 		result = get_valid_clk(hwmgr,
1022 	if (!result &&
1025 		result = get_valid_clk(hwmgr,
1029 	return result;
1063 	int result = 0;
1122 		result = get_vddc_lookup_table(hwmgr,
1131 		result = get_vddc_lookup_table(hwmgr,
1140 		result = get_vddc_lookup_table(hwmgr,
1144 	return result;
1149 	int result = 0;
1162 	result = check_powerplay_tables(hwmgr, powerplay_table);
1164 	PP_ASSERT_WITH_CODE((result == 0),
1165 			    "check_powerplay_tables failed", return result);
1167 	result = set_platform_caps(hwmgr,
1170 	PP_ASSERT_WITH_CODE((result == 0),
1171 			    "set_platform_caps failed", return result);
1173 	result = init_thermal_controller(hwmgr, powerplay_table);
1175 	PP_ASSERT_WITH_CODE((result == 0),
1176 			    "init_thermal_controller failed", return result);
1178 	result = init_over_drive_limits(hwmgr, powerplay_table);
1180 	PP_ASSERT_WITH_CODE((result == 0),
1181 			    "init_over_drive_limits failed", return result);
1183 	result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1185 	PP_ASSERT_WITH_CODE((result == 0),
1186 			    "init_powerplay_extended_tables failed", return result);
1188 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
1190 	PP_ASSERT_WITH_CODE((result == 0),
1191 			    "init_dpm_2_parameters failed", return result);
1193 	return result;
1268 	uint32_t result = 0;
1271 		result |= PP_StateClassificationFlag_Boot;
1274 		result |= PP_StateClassificationFlag_Thermal;
1277 		result |= PP_StateClassificationFlag_LimitedPowerSource;
1280 		result |= PP_StateClassificationFlag_Rest;
1283 		result |= PP_StateClassificationFlag_Forced;
1286 		result |= PP_StateClassificationFlag_ACPI;
1289 		result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1291 	return result;
1299 	int result = 0;
1327 		result = call_back_func(hwmgr, (void *)state_entry, power_state,
1334 	if (!result && (power_state->classification.flags &
1336 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1338 	return result;
1343 	int result = 0;
1352 	result = check_powerplay_tables(hwmgr, powerplay_table);
1354 	PP_ASSERT_WITH_CODE((result == 0),
1355 			    "check_powerplay_tables failed", return result);
1361 	return result;