powerplay/hwmgr/vega10_processpptables.c

68 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
72 	state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
73 		le16_to_cpu(powerplay_table->usStateArrayOffset));
75 	PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
78 	PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
80 	PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
120 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
129 			(((unsigned long)powerplay_table) +
130 			le16_to_cpu(powerplay_table->usThermalControllerOffset));
132 	PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
160 	if (!powerplay_table->usFanTableOffset)
164 			(((unsigned long)powerplay_table) +
165 			le16_to_cpu(powerplay_table->usFanTableOffset));
308 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
312 			(((unsigned long) powerplay_table) +
313 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
324 	if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
330 			le32_to_cpu(powerplay_table->ulMaxODEngineClock);
332 			le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
873 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
881 			(((unsigned long) powerplay_table) +
882 			le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
885 			(((unsigned long) powerplay_table) +
886 			le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
889 			(((unsigned long) powerplay_table) +
890 			le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
893 			(((unsigned long) powerplay_table) +
894 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
897 			(((unsigned long) powerplay_table) +
898 			le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
901 			(((unsigned long) powerplay_table) +
902 			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
905 			(((unsigned long) powerplay_table) +
906 			le16_to_cpu(powerplay_table->usHardLimitTableOffset));
909 			(((unsigned long) powerplay_table) +
910 			le16_to_cpu(powerplay_table->usPCIETableOffset));
913 			(((unsigned long) powerplay_table) +
914 			le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
917 			(((unsigned long) powerplay_table) +
918 			le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
921 			(((unsigned long) powerplay_table) +
922 			le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
934 	if (powerplay_table->usMMDependencyTableOffset)
939 	if (!result && powerplay_table->usPowerTuneTableOffset)
944 	if (!result && powerplay_table->usSocclkDependencyTableOffset)
949 	if (!result && powerplay_table->usGfxclkDependencyTableOffset)
954 	if (!result && powerplay_table->usPixclkDependencyTableOffset)
960 	if (!result && powerplay_table->usPhyClkDependencyTableOffset)
966 	if (!result && powerplay_table->usDispClkDependencyTableOffset)
972 	if (!result && powerplay_table->usDcefclkDependencyTableOffset)
977 	if (!result && powerplay_table->usMclkDependencyTableOffset)
982 	if (!result && powerplay_table->usPCIETableOffset)
987 	if (!result && powerplay_table->usHardLimitTableOffset)
1061 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1069 		le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1072 			le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1074 			le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1076 			le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1078 			le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1080 			le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1082 			le16_to_cpu(powerplay_table->ucSocVoltageMode);
1084 			le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1086 			le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1088 			le16_to_cpu(powerplay_table->ucVceVoltageMode);
1090 			le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1092 			le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1101 		le16_to_cpu(powerplay_table->usPowerControlLimit);
1117 	if (powerplay_table->usVddcLookupTableOffset) {
1120 				(((unsigned long)powerplay_table) +
1121 				le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1126 	if (powerplay_table->usVddmemLookupTableOffset) {
1129 				(((unsigned long)powerplay_table) +
1130 				le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1135 	if (powerplay_table->usVddciLookupTableOffset) {
1138 				(((unsigned long)powerplay_table) +
1139 				le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1150 	const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1157 	powerplay_table = get_powerplay_table(hwmgr);
1159 	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1162 	result = check_powerplay_tables(hwmgr, powerplay_table);
1168 				   le32_to_cpu(powerplay_table->ulPlatformCaps));
1173 	result = init_thermal_controller(hwmgr, powerplay_table);
1178 	result = init_over_drive_limits(hwmgr, powerplay_table);
1183 	result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1188 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
1345 	const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1347 	powerplay_table = get_powerplay_table(hwmgr);
1349 	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1352 	result = check_powerplay_tables(hwmgr, powerplay_table);
1359 			0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),