powerplay/hwmgr/vega10_hwmgr.c

332 	dep_table[1] = table_info->vdd_dep_on_mclk;
335 	od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
668 			table_info->vdd_dep_on_mclk;
773 			table_info->vdd_dep_on_mclk;
1169 				table_info->vdd_dep_on_mclk,
1178 				table_info->vdd_dep_on_mclk,
1309 			table_info->vdd_dep_on_mclk;
1821 					&data->odn_dpm_table.vdd_dep_on_mclk;
1823 		dep_on_mclk = table_info->vdd_dep_on_mclk;
2519 	dep_table = table_info->vdd_dep_on_mclk;
2520 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
3013 	    table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3015 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3018 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;
3022 	hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;
3473 	odn_clk_table = &odn_table->vdd_dep_on_mclk;
3609 	vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
4067 	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4190 		table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4209 		*mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4393 			table_info->vdd_dep_on_mclk;
4480 		dep_table = table_info->vdd_dep_on_mclk;
4763 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4896 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5483 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5561 		podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;