powerplay/hwmgr/smu_helper.c

27 #include "hwmgr.h"
47 	struct pp_hwmgr *hwmgr,
69 	struct pp_hwmgr *hwmgr,
110 int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
116 	if (hwmgr == NULL || hwmgr->device == NULL) {
121 	for (i = 0; i < hwmgr->usec_timeout; i++) {
122 		cur_value = cgs_read_register(hwmgr->device, index);
129 	if (i == hwmgr->usec_timeout)
140 int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
146 	if (hwmgr == NULL || hwmgr->device == NULL) {
151 	cgs_write_register(hwmgr->device, indirect_port, index);
152 	return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
155 int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
162 	if (hwmgr == NULL || hwmgr->device == NULL)
165 	for (i = 0; i < hwmgr->usec_timeout; i++) {
166 		cur_value = cgs_read_register(hwmgr->device,
174 	if (i == hwmgr->usec_timeout)
179 int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
185 	if (hwmgr == NULL || hwmgr->device == NULL)
188 	cgs_write_register(hwmgr->device, indirect_port, index);
189 	return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
193 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
195 	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
198 bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
200 	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
460 int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
467 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
491  * @hwmgr:  the address of the powerplay hardware manager.
493 int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
496 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
508 		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
509 		    hwmgr->chip_id <= CHIP_VEGAM)
514 		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
515 		    hwmgr->chip_id <= CHIP_VEGAM)
520 		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
521 		    hwmgr->chip_id <= CHIP_VEGAM)
529 		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
535 uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
545 void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
548 			(struct phm_ppt_v1_information *)hwmgr->pptable;
552 	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
571 			smum_send_msg_to_smc_with_parameter(hwmgr,
582 int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
588 	if (hwmgr->chip_id < CHIP_TONGA) {
589 		ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
590 	} else if (hwmgr->chip_id < CHIP_POLARIS10) {
591 		ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
595 		ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
606 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
612 			schedule_delayed_work(&hwmgr->swctf_delayed_work,
626 			schedule_delayed_work(&hwmgr->swctf_delayed_work,
646 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
656 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
660 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
666 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),