Lines Matching defs:ps
1341 struct pp_power_state *ps;
1347 ps = hwmgr->request_ps;
1349 if (ps == NULL)
1352 smu8_ps = cast_smu8_power_state(&ps->hardware);
1415 unsigned long entry, struct pp_power_state *ps)
1420 ps->hardware.magic = smu8_magic;
1422 smu8_ps = cast_smu8_power_state(&(ps->hardware));
1424 result = pp_tables_get_entry(hwmgr, entry, ps,
1427 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1428 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1600 const struct smu8_power_state *ps;
1609 ps = cast_const_smu8_power_state(state);
1611 level_index = index > ps->level - 1 ? ps->level - 1 : index;
1612 level->coreClock = ps->levels[level_index].engineClock;
1615 for (i = 1; i < ps->level; i++) {
1616 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1617 level->coreClock = ps->levels[i].engineClock;
1628 level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1638 const struct smu8_power_state *ps = cast_const_smu8_power_state(state);
1640 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1641 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));