powerplay/hwmgr/smu7_powertune.c

24 #include "hwmgr.h"
850 static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
852 	struct amdgpu_device *adev = hwmgr->adev;
858 	if ((hwmgr->chip_id == CHIP_POLARIS11) &&
865 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
871 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
877 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
883 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
889 		result = smum_send_msg_to_smc_with_parameter(hwmgr,
897 static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
912 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
916 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
920 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
924 				data = cgs_read_register(hwmgr->device, config_regs->offset);
934 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data);
938 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
942 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
946 				cgs_write_register(hwmgr->device, config_regs->offset, data);
958 int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
963 	struct amdgpu_device *adev = hwmgr->adev;
976 		value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
981 			cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
983 			if (hwmgr->chip_id == CHIP_POLARIS10) {
984 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
986 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
988 			} else if (hwmgr->chip_id == CHIP_POLARIS11) {
989 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
994 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
996 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
998 			} else if (hwmgr->chip_id == CHIP_POLARIS12) {
999 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
1001 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12);
1003 			} else if (hwmgr->chip_id == CHIP_VEGAM) {
1004 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM);
1006 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM);
1010 		cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
1012 		result = smu7_enable_didt(hwmgr, true);
1015 		if (hwmgr->chip_id == CHIP_POLARIS11) {
1016 			result = smum_send_msg_to_smc(hwmgr,
1024 				result = smum_send_msg_to_smc(hwmgr,
1030 				atomctrl_read_efuse(hwmgr, 547, 547, &efuse);
1032 					result = smum_send_msg_to_smc(hwmgr,
1038 					result = smum_send_msg_to_smc(hwmgr,
1058 int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
1061 	struct amdgpu_device *adev = hwmgr->adev;
1070 		result = smu7_enable_didt(hwmgr, false);
1074 		if (hwmgr->chip_id == CHIP_POLARIS11) {
1075 			result = smum_send_msg_to_smc(hwmgr,
1090 int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
1092 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1097 		smc_result = smum_send_msg_to_smc(hwmgr,
1108 int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
1110 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1114 		int smc_result = smum_send_msg_to_smc(hwmgr,
1125 int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1127 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1131 		return smum_send_msg_to_smc_with_parameter(hwmgr,
1138 static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
1141 	return smum_send_msg_to_smc_with_parameter(hwmgr,
1147 int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
1149 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1151 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
1157 	if (hwmgr->pp_table_version == PP_TABLE_V1)
1160 		cac_table = hwmgr->dyn_state.cac_dtp_table;
1164 			smc_result = smum_send_msg_to_smc(hwmgr,
1175 			smc_result = smum_send_msg_to_smc(hwmgr,
1181 				hwmgr->default_power_limit = hwmgr->power_limit =
1186 				if (smu7_set_power_limit(hwmgr, hwmgr->power_limit))
1194 int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
1196 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1205 			smc_result = smum_send_msg_to_smc(hwmgr,
1215 			smc_result = smum_send_msg_to_smc(hwmgr,
1225 			smc_result = smum_send_msg_to_smc(hwmgr,
1238 int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
1241 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
1247 	if (hwmgr->pp_table_version == PP_TABLE_V1)
1250 		cac_table = hwmgr->dyn_state.cac_dtp_table;
1253 		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1254 				hwmgr->platform_descriptor.TDPAdjustment :
1255 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
1257 		if (hwmgr->chip_id > CHIP_TONGA)
1262 		result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);