Lines Matching defs:hwmgr
35 #include "hwmgr.h"
50 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr,
74 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,
77 uint16_t table_offset = get_vce_table_offset(hwmgr,
86 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,
89 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
102 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,
105 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
109 return table_offset + get_vce_clock_info_array_size(hwmgr,
115 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,
118 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
130 static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
132 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
135 return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);
141 struct pp_hwmgr *hwmgr,
144 uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);
152 static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr,
174 static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr,
177 uint16_t table_offset = get_uvd_table_offset(hwmgr,
185 static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr,
188 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
204 struct pp_hwmgr *hwmgr,
207 uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
212 get_uvd_clock_info_array_size(hwmgr, powerplay_table);
217 static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr,
241 struct pp_hwmgr *hwmgr,
244 uint16_t table_offset = get_samu_table_offset(hwmgr,
253 static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr,
277 struct pp_hwmgr *hwmgr,
280 uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table);
289 struct pp_hwmgr *hwmgr,
312 static int get_cac_tdp_table(struct pp_hwmgr *hwmgr,
340 static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr,
365 struct pp_hwmgr *hwmgr,
368 uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table);
377 static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
405 static int get_valid_clk(struct pp_hwmgr *hwmgr,
426 static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr,
441 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
445 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
447 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
450 static int set_platform_caps(struct pp_hwmgr *hwmgr,
454 hwmgr,
460 hwmgr,
466 hwmgr,
472 hwmgr,
478 hwmgr,
484 hwmgr,
490 hwmgr,
496 hwmgr,
502 hwmgr,
508 hwmgr,
514 hwmgr,
520 hwmgr,
526 hwmgr,
532 hwmgr,
538 hwmgr,
544 hwmgr,
550 hwmgr,
556 hwmgr,
562 hwmgr,
568 hwmgr,
574 hwmgr,
580 hwmgr,
586 hwmgr,
592 hwmgr,
598 hwmgr,
604 hwmgr,
610 hwmgr,
619 struct pp_hwmgr *hwmgr,
676 static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
685 ps->classification.flags = make_classification_flags(hwmgr,
826 struct pp_hwmgr *hwmgr)
828 const void *table_addr = hwmgr->soft_pp_table;
833 if (hwmgr->chip_id == CHIP_RAVEN) {
835 hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
836 hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
838 table_addr = smu_atom_get_data_table(hwmgr->adev,
841 hwmgr->soft_pp_table = table_addr;
842 hwmgr->soft_pp_table_size = size;
849 int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,
852 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr);
863 int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
867 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
883 int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
892 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
924 result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info);
930 res = func(hwmgr, &ps->hardware, i, pclock_info);
947 result = init_non_clock_fields(hwmgr, ps,
957 int res = func(hwmgr, &ps->hardware, i, pclock_info);
965 if (hwmgr->chip_family < AMDGPU_FAMILY_RV)
966 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
973 struct pp_hwmgr *hwmgr,
982 struct pp_hwmgr *hwmgr,
985 struct amdgpu_device *adev = hwmgr->adev;
987 hwmgr->thermal_controller.ucType =
989 hwmgr->thermal_controller.ucI2cLine =
991 hwmgr->thermal_controller.ucI2cAddress =
994 hwmgr->thermal_controller.fanInfo.bNoFan =
998 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
1002 hwmgr->thermal_controller.fanInfo.ulMinRPM
1004 hwmgr->thermal_controller.fanInfo.ulMaxRPM
1007 set_hw_cap(hwmgr,
1008 ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
1016 hwmgr->thermal_controller.use_hw_fan_control = 1;
1024 hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst =
1026 hwmgr->thermal_controller.advanceFanControlParameters.usTMin =
1028 hwmgr->thermal_controller.advanceFanControlParameters.usTMed =
1030 hwmgr->thermal_controller.advanceFanControlParameters.usTHigh =
1032 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
1034 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed =
1036 hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh =
1038 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 10900;
1039 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay = 100000;
1041 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1049 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
1058 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode =
1063 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
1066 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
1069 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity =
1071 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1080 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1083 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM =
1095 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1097 hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentLow =
1099 hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentHigh =
1101 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMLow =
1103 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMHigh =
1113 static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr,
1117 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1120 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1123 hwmgr->platform_descriptor.maxOverdriveVDDC =
1126 hwmgr->platform_descriptor.minOverdriveVDDC =
1129 hwmgr->platform_descriptor.maxOverdriveVDDC =
1132 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
1136 static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr,
1155 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock);
1156 hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock);
1159 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
1160 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
1161 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
1166 static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
1175 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0;
1176 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;
1177 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
1178 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
1179 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
1181 if (hwmgr->chip_id == CHIP_RAVEN)
1185 fw_info = smu_atom_get_data_table(hwmgr->adev,
1191 result = init_overdrive_limits_V1_4(hwmgr,
1197 result = init_overdrive_limits_V2_1(hwmgr,
1204 static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1234 static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1263 static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1288 static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
1313 static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
1324 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
1325 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
1326 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
1327 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1328 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
1329 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
1330 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
1331 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
1332 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
1333 hwmgr->dyn_state.ppm_parameter_table = NULL;
1334 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
1337 hwmgr, powerplay_table);
1338 table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,
1347 result = get_vce_clock_voltage_limit_table(hwmgr,
1348 &hwmgr->dyn_state.vce_clock_voltage_dependency_table,
1352 uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table);
1353 table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
1362 result = get_uvd_clock_voltage_limit_table(hwmgr,
1363 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array);
1366 table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
1373 result = get_samu_clock_voltage_limit_table(hwmgr,
1374 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable);
1377 table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,
1384 result = get_acp_clock_voltage_limit_table(hwmgr,
1385 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable);
1388 table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);
1396 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table,
1399 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
1405 result = get_cac_tdp_table(hwmgr,
1406 &hwmgr->dyn_state.cac_dtp_table,
1419 result = get_clock_voltage_dependency_table(hwmgr,
1420 &hwmgr->dyn_state.vddc_dependency_on_sclk, table);
1427 result = get_clock_voltage_dependency_table(hwmgr,
1428 &hwmgr->dyn_state.vddci_dependency_on_mclk, table);
1435 result = get_clock_voltage_dependency_table(hwmgr,
1436 &hwmgr->dyn_state.vddc_dependency_on_mclk, table);
1443 result = get_clock_voltage_limit(hwmgr,
1444 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table);
1447 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&
1448 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))
1449 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values,
1450 hwmgr->dyn_state.vddc_dependency_on_mclk);
1452 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) &&
1453 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count))
1454 result = get_valid_clk(hwmgr,
1455 &hwmgr->dyn_state.valid_sclk_values,
1456 hwmgr->dyn_state.vddc_dependency_on_sclk);
1462 result = get_clock_voltage_dependency_table(hwmgr,
1463 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table);
1467 table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,
1473 result = get_clock_voltage_dependency_table(hwmgr,
1474 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);
1480 static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
1487 if (!hwmgr || !table || !ptable)
1498 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1514 static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,
1532 hwmgr->dyn_state.ppm_parameter_table = ptr;
1537 static int init_dpm2_parameters(struct pp_hwmgr *hwmgr,
1556 hwmgr->platform_descriptor.TDPLimit = le32_to_cpu(ptable5->ulTDPLimit);
1557 hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit);
1559 hwmgr->platform_descriptor.TDPODLimit = le16_to_cpu(ptable5->usTDPODLimit);
1560 hwmgr->platform_descriptor.TDPAdjustment = 0;
1562 hwmgr->platform_descriptor.VidAdjustment = 0;
1563 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1564 hwmgr->platform_descriptor.VidMinLimit = 0;
1565 hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1566 hwmgr->platform_descriptor.VidStep = 6250;
1568 hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit);
1570 if (hwmgr->platform_descriptor.TDPODLimit != 0)
1571 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1574 hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold);
1576 hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage);
1578 hwmgr->dyn_state.cac_leakage_table = NULL;
1584 result = get_cac_leakage_table(hwmgr,
1585 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table);
1588 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope);
1590 hwmgr->dyn_state.ppm_parameter_table = NULL;
1602 if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table))
1603 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1611 static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
1642 hwmgr->dyn_state.vddc_phase_shed_limits_table = table;
1650 struct pp_hwmgr *hwmgr)
1653 get_powerplay_table(hwmgr);
1655 get_vce_state_table(hwmgr, table);
1663 static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
1669 const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
1671 const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table);
1673 unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_table);
1697 static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
1702 if (hwmgr->chip_id == CHIP_RAVEN)
1705 hwmgr->need_pp_table_upload = true;
1707 powerplay_table = get_powerplay_table(hwmgr);
1709 result = init_powerplay_tables(hwmgr, powerplay_table);
1714 result = set_platform_caps(hwmgr,
1720 result = init_thermal_controller(hwmgr, powerplay_table);
1725 result = init_overdrive_limits(hwmgr, powerplay_table);
1730 result = init_clock_voltage_dependency(hwmgr,
1736 result = init_dpm2_parameters(hwmgr, powerplay_table);
1741 result = init_phase_shedding_table(hwmgr, powerplay_table);
1749 static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1751 if (hwmgr->chip_id == CHIP_RAVEN)
1754 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
1755 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
1757 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
1758 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
1760 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
1761 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
1763 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
1764 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
1766 kfree(hwmgr->dyn_state.valid_mclk_values);
1767 hwmgr->dyn_state.valid_mclk_values = NULL;
1769 kfree(hwmgr->dyn_state.valid_sclk_values);
1770 hwmgr->dyn_state.valid_sclk_values = NULL;
1772 kfree(hwmgr->dyn_state.cac_leakage_table);
1773 hwmgr->dyn_state.cac_leakage_table = NULL;
1775 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
1776 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
1778 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
1779 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
1781 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
1782 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
1784 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
1785 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
1787 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
1788 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
1790 kfree(hwmgr->dyn_state.cac_dtp_table);
1791 hwmgr->dyn_state.cac_dtp_table = NULL;
1793 kfree(hwmgr->dyn_state.ppm_parameter_table);
1794 hwmgr->dyn_state.ppm_parameter_table = NULL;
1796 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
1797 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;