powerplay/hwmgr/hwmgr.c

32 #include "hwmgr.h"
50 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
52 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
53 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
54 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
55 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
56 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
57 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
58 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
61 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
63 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
64 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
65 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
66 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
67 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
68 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
70 	hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
71 	hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
72 	hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
73 	hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
74 	hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
75 	hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
78 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
82 	if (!hwmgr)
85 	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
86 	hwmgr->pp_table_version = PP_TABLE_V1;
87 	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
88 	hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
89 	hwmgr_init_default_caps(hwmgr);
90 	hwmgr_set_user_specify_caps(hwmgr);
91 	hwmgr->fan_ctrl_is_in_default_mode = true;
92 	hwmgr_init_workload_prority(hwmgr);
93 	hwmgr->gfxoff_state_changed_by_workload = false;
95 	adev = hwmgr->adev;
97 	switch (hwmgr->chip_family) {
100 		hwmgr->smumgr_funcs = &ci_smu_funcs;
101 		ci_set_asic_special_caps(hwmgr);
102 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
105 		hwmgr->pp_table_version = PP_TABLE_V0;
106 		hwmgr->od_enabled = false;
107 		smu7_init_function_pointers(hwmgr);
111 		hwmgr->od_enabled = false;
112 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
113 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
114 		smu8_init_function_pointers(hwmgr);
118 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
119 		switch (hwmgr->chip_id) {
121 			hwmgr->smumgr_funcs = &iceland_smu_funcs;
122 			topaz_set_asic_special_caps(hwmgr);
123 			hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
125 			hwmgr->pp_table_version = PP_TABLE_V0;
126 			hwmgr->od_enabled = false;
129 			hwmgr->smumgr_funcs = &tonga_smu_funcs;
130 			tonga_set_asic_special_caps(hwmgr);
131 			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
134 			hwmgr->smumgr_funcs = &fiji_smu_funcs;
135 			fiji_set_asic_special_caps(hwmgr);
136 			hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
142 			hwmgr->smumgr_funcs = &polaris10_smu_funcs;
143 			polaris_set_asic_special_caps(hwmgr);
144 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
147 			hwmgr->smumgr_funcs = &vegam_smu_funcs;
148 			polaris_set_asic_special_caps(hwmgr);
149 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
154 		smu7_init_function_pointers(hwmgr);
157 		switch (hwmgr->chip_id) {
160 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
161 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
162 			vega10_hwmgr_init(hwmgr);
165 			hwmgr->smumgr_funcs = &vega12_smu_funcs;
166 			vega12_hwmgr_init(hwmgr);
170 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
171 			hwmgr->smumgr_funcs = &vega20_smu_funcs;
172 			vega20_hwmgr_init(hwmgr);
179 		switch (hwmgr->chip_id) {
181 			hwmgr->od_enabled = false;
182 			hwmgr->smumgr_funcs = &smu10_smu_funcs;
183 			smu10_init_function_pointers(hwmgr);
196 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
198 	if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
201 	phm_register_irq_handlers(hwmgr);
202 	pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name);
204 	return hwmgr->smumgr_funcs->smu_init(hwmgr);
208 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
210 	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
211 		hwmgr->smumgr_funcs->smu_fini(hwmgr);
216 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
220 	hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device *)hwmgr->adev);
221 	hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf))
223 	if (!hwmgr->pm_en)
226 	if (!hwmgr->pptable_func ||
227 	    !hwmgr->pptable_func->pptable_init ||
228 	    !hwmgr->hwmgr_func->backend_init) {
229 		hwmgr->pm_en = false;
234 	ret = hwmgr->pptable_func->pptable_init(hwmgr);
238 	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
239 				hwmgr->thermal_controller.fanInfo.bNoFan;
241 	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
245 	if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
246 			(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
247 			hwmgr->dyn_state.max_clock_voltage_on_dc =
248 					hwmgr->dyn_state.max_clock_voltage_on_ac;
250 	ret = psm_init_power_state_table(hwmgr);
254 	ret = phm_setup_asic(hwmgr);
258 	ret = phm_enable_dynamic_state_management(hwmgr);
261 	ret = phm_start_thermal_controller(hwmgr);
262 	ret |= psm_set_performance_states(hwmgr);
266 	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
270 	if (hwmgr->hwmgr_func->backend_fini)
271 		hwmgr->hwmgr_func->backend_fini(hwmgr);
273 	if (hwmgr->pptable_func->pptable_fini)
274 		hwmgr->pptable_func->pptable_fini(hwmgr);
279 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
281 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
284 	phm_stop_thermal_controller(hwmgr);
285 	psm_set_boot_states(hwmgr);
286 	psm_adjust_power_state_dynamic(hwmgr, true, NULL);
287 	phm_disable_dynamic_state_management(hwmgr);
288 	phm_disable_clock_power_gatings(hwmgr);
290 	if (hwmgr->hwmgr_func->backend_fini)
291 		hwmgr->hwmgr_func->backend_fini(hwmgr);
292 	if (hwmgr->pptable_func->pptable_fini)
293 		hwmgr->pptable_func->pptable_fini(hwmgr);
294 	return psm_fini_power_state_table(hwmgr);
297 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
301 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
304 	phm_disable_smc_firmware_ctf(hwmgr);
305 	ret = psm_set_boot_states(hwmgr);
308 	ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
311 	ret = phm_power_down_asic(hwmgr);
316 int hwmgr_resume(struct pp_hwmgr *hwmgr)
320 	if (!hwmgr)
323 	if (!hwmgr->not_vf || !hwmgr->pm_en)
326 	ret = phm_setup_asic(hwmgr);
330 	ret = phm_enable_dynamic_state_management(hwmgr);
333 	ret = phm_start_thermal_controller(hwmgr);
334 	ret |= psm_set_performance_states(hwmgr);
338 	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
357 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
362 	if (hwmgr == NULL)
367 		if (!hwmgr->not_vf)
369 		ret = phm_pre_display_configuration_changed(hwmgr);
372 		ret = phm_set_cpu_power_state(hwmgr);
375 		ret = psm_set_performance_states(hwmgr);
378 		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
385 		if (!hwmgr->not_vf)
393 		ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
396 		ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);
401 		ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
409 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
411 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
413 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
414 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
417 	if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
418 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
421 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
424 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
427 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
430 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
433 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
436 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
441 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
443 	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
444 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
447 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
450 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
451 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
453 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
456 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
458 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
462 	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
463 		hwmgr->od_enabled = true;
468 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
470 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
472 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
474 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
477 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
479 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
482 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
485 	if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
486 	    (hwmgr->chip_id == CHIP_POLARIS12))
487 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
490 	if (hwmgr->chip_id != CHIP_POLARIS11) {
491 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
493 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
495 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
501 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
503 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
505 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
507 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
509 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
511 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
516 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
518 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
520 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
522 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
524 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
526 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
529 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
531 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
536 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
538 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
540 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
542 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
544 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
546 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
551 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
553 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
555 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
557 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
559 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
561 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
563 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,