pm/powerplay/amd_powerplay.c

34 #include "hwmgr.h"
42 	struct pp_hwmgr *hwmgr;
47 	hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
48 	if (hwmgr == NULL)
51 	hwmgr->adev = adev;
52 	hwmgr->not_vf = !amdgpu_sriov_vf(adev);
53 	hwmgr->device = amdgpu_cgs_create_device(adev);
54 	mutex_init(&hwmgr->msg_lock);
55 	hwmgr->chip_family = adev->family;
56 	hwmgr->chip_id = adev->asic_type;
57 	hwmgr->feature_mask = adev->pm.pp_feature;
58 	hwmgr->display_config = &adev->pm.pm_display_cfg;
59 	adev->powerplay.pp_handle = hwmgr;
67 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
69 	mutex_destroy(&hwmgr->msg_lock);
71 	kfree(hwmgr->hardcode_pp_table);
72 	hwmgr->hardcode_pp_table = NULL;
74 	kfree(hwmgr);
75 	hwmgr = NULL;
97 	struct pp_hwmgr *hwmgr =
99 	struct amdgpu_device *adev = hwmgr->adev;
111 	    hwmgr->hwmgr_func->read_sensor) {
112 		ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
121 			ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
137 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
140 	ret = hwmgr_sw_init(hwmgr);
145 		INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work,
154 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
156 	hwmgr_sw_fini(hwmgr);
167 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
169 	ret = hwmgr_hw_init(hwmgr);
180 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
182 	cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
184 	hwmgr_hw_fini(hwmgr);
194 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
205 	if (hwmgr->hwmgr_func->notify_cac_buffer_info)
206 		r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
223 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
225 	if (hwmgr && hwmgr->pm_en)
226 		hwmgr_handle_task(hwmgr,
268 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
270 	cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
272 	return hwmgr_suspend(hwmgr);
278 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
280 	return hwmgr_resume(hwmgr);
325 	struct pp_hwmgr *hwmgr = handle;
327 	if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
330 	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
345 	struct pp_hwmgr *hwmgr = handle;
347 	if (!hwmgr || !hwmgr->pm_en)
350 	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
355 	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
358 static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
366 	if (!(hwmgr->dpm_level & profile_mode_mask)) {
369 			hwmgr->saved_dpm_level = hwmgr->dpm_level;
370 			hwmgr->en_umd_pstate = true;
376 				*level = hwmgr->saved_dpm_level;
377 			hwmgr->en_umd_pstate = false;
385 	struct pp_hwmgr *hwmgr = handle;
387 	if (!hwmgr || !hwmgr->pm_en)
390 	if (level == hwmgr->dpm_level)
393 	pp_dpm_en_umd_pstate(hwmgr, &level);
394 	hwmgr->request_dpm_level = level;
395 	hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
403 	struct pp_hwmgr *hwmgr = handle;
405 	if (!hwmgr || !hwmgr->pm_en)
408 	return hwmgr->dpm_level;
413 	struct pp_hwmgr *hwmgr = handle;
415 	if (!hwmgr || !hwmgr->pm_en)
418 	if (hwmgr->hwmgr_func->get_sclk == NULL) {
422 	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
427 	struct pp_hwmgr *hwmgr = handle;
429 	if (!hwmgr || !hwmgr->pm_en)
432 	if (hwmgr->hwmgr_func->get_mclk == NULL) {
436 	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
441 	struct pp_hwmgr *hwmgr = handle;
443 	if (!hwmgr || !hwmgr->pm_en)
446 	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
450 	hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
455 	struct pp_hwmgr *hwmgr = handle;
457 	if (!hwmgr || !hwmgr->pm_en)
460 	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
464 	hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
470 	struct pp_hwmgr *hwmgr = handle;
472 	if (!hwmgr || !hwmgr->pm_en)
475 	return hwmgr_handle_task(hwmgr, task_id, user_state);
480 	struct pp_hwmgr *hwmgr = handle;
484 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
487 	state = hwmgr->current_ps;
512 	struct pp_hwmgr *hwmgr = handle;
514 	if (!hwmgr || !hwmgr->pm_en)
517 	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL)
523 	hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
530 	struct pp_hwmgr *hwmgr = handle;
532 	if (!hwmgr || !hwmgr->pm_en)
535 	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL)
541 	*fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
547 	struct pp_hwmgr *hwmgr = handle;
549 	if (!hwmgr || !hwmgr->pm_en)
552 	if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL)
558 	return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed);
563 	struct pp_hwmgr *hwmgr = handle;
565 	if (!hwmgr || !hwmgr->pm_en)
568 	if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL)
574 	return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed);
579 	struct pp_hwmgr *hwmgr = handle;
581 	if (!hwmgr || !hwmgr->pm_en)
584 	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
590 	return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
595 	struct pp_hwmgr *hwmgr = handle;
597 	if (!hwmgr || !hwmgr->pm_en)
600 	if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL)
606 	return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
612 	struct pp_hwmgr *hwmgr = handle;
617 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps)
620 	data->nums = hwmgr->num_ps;
622 	for (i = 0; i < hwmgr->num_ps; i++) {
624 				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
647 	struct pp_hwmgr *hwmgr = handle;
649 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->soft_pp_table)
652 	*table = (char *)hwmgr->soft_pp_table;
653 	return hwmgr->soft_pp_table_size;
658 	struct pp_hwmgr *hwmgr = handle;
661 	ret = hwmgr_hw_fini(hwmgr);
665 	ret = hwmgr_hw_init(hwmgr);
669 	return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
674 	struct pp_hwmgr *hwmgr = handle;
677 	if (!hwmgr || !hwmgr->pm_en)
680 	if (!hwmgr->hardcode_pp_table) {
681 		hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
682 						   hwmgr->soft_pp_table_size,
684 		if (!hwmgr->hardcode_pp_table)
688 	memcpy(hwmgr->hardcode_pp_table, buf, size);
690 	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
696 	if (hwmgr->hwmgr_func->avfs_control)
697 		ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
705 	struct pp_hwmgr *hwmgr = handle;
707 	if (!hwmgr || !hwmgr->pm_en)
710 	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
715 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
720 	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
728 	struct pp_hwmgr *hwmgr = handle;
730 	if (!hwmgr || !hwmgr->pm_en)
733 	if (!hwmgr->hwmgr_func->emit_clock_levels)
736 	return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset);
742 	struct pp_hwmgr *hwmgr = handle;
744 	if (!hwmgr || !hwmgr->pm_en)
747 	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
751 	return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
756 	struct pp_hwmgr *hwmgr = handle;
758 	if (!hwmgr || !hwmgr->pm_en)
761 	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
765 	return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
770 	struct pp_hwmgr *hwmgr = handle;
772 	if (!hwmgr || !hwmgr->pm_en)
775 	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
780 	return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
785 	struct pp_hwmgr *hwmgr = handle;
787 	if (!hwmgr || !hwmgr->pm_en)
790 	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
794 	return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
799 	struct pp_hwmgr *hwmgr = handle;
801 	if (!hwmgr || !hwmgr->pm_en)
804 	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
808 	return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
814 	struct pp_hwmgr *hwmgr = handle;
816 	if (!hwmgr || !hwmgr->pm_en || !value)
821 		*((uint32_t *)value) = hwmgr->pstate_sclk * 100;
824 		*((uint32_t *)value) = hwmgr->pstate_mclk * 100;
827 		*((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;
830 		*((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;
833 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
836 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
839 		return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
846 	struct pp_hwmgr *hwmgr = handle;
848 	if (!hwmgr || !hwmgr->pm_en)
851 	if (idx < hwmgr->num_vce_state_tables)
852 		return &hwmgr->vce_states[idx];
858 	struct pp_hwmgr *hwmgr = handle;
860 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode)
865 	return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
870 	struct pp_hwmgr *hwmgr = handle;
872 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode)
875 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
880 	return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
885 	struct pp_hwmgr *hwmgr = handle;
887 	if (!hwmgr || !hwmgr->pm_en)
890 	if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL)
893 	return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
899 	struct pp_hwmgr *hwmgr = handle;
901 	if (!hwmgr || !hwmgr->pm_en)
904 	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
909 	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
914 	struct pp_hwmgr *hwmgr = handle;
916 	if (!hwmgr)
919 	if (!hwmgr->pm_en)
922 	if (hwmgr->hwmgr_func->set_mp1_state)
923 		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
931 	struct pp_hwmgr *hwmgr = handle;
935 	if (!hwmgr || !hwmgr->pm_en)
938 	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
947 		hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
948 		index = fls(hwmgr->workload_mask);
950 		workload = hwmgr->workload_setting[index];
952 		hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
953 		index = fls(hwmgr->workload_mask);
955 		workload = hwmgr->workload_setting[index];
959 		hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
960 			if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en))
964 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
965 		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
972 	struct pp_hwmgr *hwmgr = handle;
975 	if (!hwmgr || !hwmgr->pm_en)
978 	if (hwmgr->hwmgr_func->set_power_limit == NULL) {
984 		limit = hwmgr->default_power_limit;
986 	max_power_limit = hwmgr->default_power_limit;
987 	if (hwmgr->od_enabled) {
988 		max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
995 	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
996 	hwmgr->power_limit = limit;
1004 	struct pp_hwmgr *hwmgr = handle;
1007 	if (!hwmgr || !hwmgr->pm_en || !limit)
1015 			*limit = hwmgr->power_limit;
1018 			*limit = hwmgr->default_power_limit;
1021 			*limit = hwmgr->default_power_limit;
1022 			if (hwmgr->od_enabled) {
1023 				*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1041 	struct pp_hwmgr *hwmgr = handle;
1043 	if (!hwmgr || !hwmgr->pm_en)
1046 	phm_store_dal_configuration_data(hwmgr, display_config);
1053 	struct pp_hwmgr *hwmgr = handle;
1055 	if (!hwmgr || !hwmgr->pm_en || !output)
1058 	return phm_get_dal_power_level(hwmgr, output);
1066 	struct pp_hwmgr *hwmgr = handle;
1069 	if (!hwmgr || !hwmgr->pm_en)
1072 	phm_get_dal_power_level(hwmgr, &simple_clocks);
1074 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1076 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1079 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1102 	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1111 	struct pp_hwmgr *hwmgr = handle;
1113 	if (!hwmgr || !hwmgr->pm_en)
1119 	return phm_get_clock_by_type(hwmgr, type, clocks);
1126 	struct pp_hwmgr *hwmgr = handle;
1128 	if (!hwmgr || !hwmgr->pm_en || !clocks)
1131 	return phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1138 	struct pp_hwmgr *hwmgr = handle;
1140 	if (!hwmgr || !hwmgr->pm_en || !clocks)
1143 	return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1149 	struct pp_hwmgr *hwmgr = handle;
1151 	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1154 	return phm_set_watermarks_for_clocks_ranges(hwmgr,
1161 	struct pp_hwmgr *hwmgr = handle;
1163 	if (!hwmgr || !hwmgr->pm_en || !clock)
1166 	return phm_display_clock_voltage_request(hwmgr, clock);
1172 	struct pp_hwmgr *hwmgr = handle;
1175 	if (!hwmgr || !hwmgr->pm_en || !clocks)
1180 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1181 		ret = phm_get_max_high_clocks(hwmgr, clocks);
1188 	struct pp_hwmgr *hwmgr = handle;
1190 	if (!hwmgr || !hwmgr->pm_en)
1193 	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
1198 	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1203 	struct pp_hwmgr *hwmgr = handle;
1205 	if (!hwmgr || !hwmgr->pm_en)
1208 	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
1213 	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1218 	struct pp_hwmgr *hwmgr = handle;
1220 	if (!hwmgr || !hwmgr->pm_en)
1223 	if (hwmgr->hwmgr_func->powergate_acp == NULL) {
1228 	hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1233 	struct pp_hwmgr *hwmgr = handle;
1235 	if (!hwmgr)
1238 	if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
1243 	hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1284 	struct pp_hwmgr *hwmgr = handle;
1286 	if (!hwmgr || !hwmgr->pm_en)
1289 	if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
1294 	hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1301 	struct pp_hwmgr *hwmgr = handle;
1303 	if (!hwmgr)
1306 	if (!hwmgr->pm_en ||
1307 	     hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1310 	hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1317 	struct pp_hwmgr *hwmgr = handle;
1319 	if (!hwmgr || !hwmgr->pm_en)
1322 	if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
1327 	hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1334 	struct pp_hwmgr *hwmgr = handle;
1336 	if (!hwmgr || !hwmgr->pm_en)
1339 	if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
1344 	hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1351 	struct pp_hwmgr *hwmgr = handle;
1353 	if (!hwmgr || !hwmgr->pm_en)
1356 	if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
1361 	hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1368 	struct pp_hwmgr *hwmgr = handle;
1370 	if (!hwmgr || !hwmgr->pm_en)
1373 	return phm_set_active_display_count(hwmgr, count);
1378 	struct pp_hwmgr *hwmgr = handle;
1380 	if (!hwmgr)
1383 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1384 		!hwmgr->hwmgr_func->get_bamaco_support)
1387 	return hwmgr->hwmgr_func->get_bamaco_support(hwmgr);
1392 	struct pp_hwmgr *hwmgr = handle;
1394 	if (!hwmgr)
1397 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1400 	hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1407 	struct pp_hwmgr *hwmgr = handle;
1409 	if (!hwmgr)
1412 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1413 		!hwmgr->hwmgr_func->set_asic_baco_state)
1416 	hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1423 	struct pp_hwmgr *hwmgr = handle;
1425 	if (!hwmgr || !hwmgr->pm_en || !buf)
1428 	if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
1433 	return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1438 	struct pp_hwmgr *hwmgr = handle;
1440 	if (!hwmgr || !hwmgr->pm_en)
1443 	if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
1448 	return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1453 	struct pp_hwmgr *hwmgr = handle;
1455 	if (!hwmgr || !hwmgr->pm_en)
1458 	if (hwmgr->hwmgr_func->asic_reset == NULL) {
1463 	return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1468 	struct pp_hwmgr *hwmgr = handle;
1470 	if (!hwmgr || !hwmgr->pm_en)
1473 	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
1478 	return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1483 	struct pp_hwmgr *hwmgr = handle;
1485 	if (!hwmgr)
1488 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1491 	hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1498 	struct pp_hwmgr *hwmgr = handle;
1500 	if (!hwmgr)
1503 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1506 	hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1513 	struct pp_hwmgr *hwmgr = handle;
1515 	if (!hwmgr)
1518 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1521 	return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1526 	struct pp_hwmgr *hwmgr = handle;
1528 	if (!hwmgr || !hwmgr->pm_en)
1531 	if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
1536 	hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1542 	struct pp_hwmgr *hwmgr = handle;
1543 	struct amdgpu_device *adev = hwmgr->adev;
1563 	struct pp_hwmgr *hwmgr = handle;
1564 	struct amdgpu_device *adev = hwmgr->adev;