pm/legacy-dpm/si_dpm.c

3144 	struct si_ps *new_ps = si_get_ps(rps);
3149 	ni_pi->current_ps = *new_ps;
3157 	struct si_ps *new_ps = si_get_ps(rps);
3162 	ni_pi->requested_ps = *new_ps;
3168 					   struct amdgpu_ps *new_ps,
3171 	struct si_ps *new_state = si_get_ps(new_ps);
3174 	if ((new_ps->vclk == old_ps->vclk) &&
3175 	    (new_ps->dclk == old_ps->dclk))
3182 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3186 					  struct amdgpu_ps *new_ps,
3189 	struct si_ps *new_state = si_get_ps(new_ps);
3192 	if ((new_ps->vclk == old_ps->vclk) &&
3193 	    (new_ps->dclk == old_ps->dclk))
3200 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
6974 	struct amdgpu_ps *new_ps = &requested_ps;
6976 	ni_update_requested_ps(adev, new_ps);
6984 	struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6993 	ret = si_populate_smc_tdp_limits(adev, new_ps);
6996 	ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7027 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7042 		si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7043 	ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7044 	ret = si_enable_power_containment(adev, new_ps, false);
7049 	ret = si_enable_smc_cac(adev, new_ps, false);
7059 	ret = si_upload_sw_state(adev, new_ps);
7075 		ret = si_upload_mc_reg_table(adev, new_ps);
7081 	ret = si_program_memory_timing_parameters(adev, new_ps);
7086 	si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7098 	ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7099 	si_set_vce_clock(adev, new_ps, old_ps);
7101 		si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7102 	ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7107 	ret = si_enable_smc_cac(adev, new_ps, true);
7112 	ret = si_enable_power_containment(adev, new_ps, true);
7131 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7133 	ni_update_current_ps(adev, new_ps);