Lines Matching defs:uint32_t
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
260 uint32_t pspdirtableoffset;
481 uint32_t firmware_revision;
482 uint32_t bootup_sclk_in10khz;
483 uint32_t bootup_mclk_in10khz;
484 uint32_t firmware_capability; // enum atombios_firmware_capability
485 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
486 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
494 uint32_t mc_baseaddr_high;
495 uint32_t mc_baseaddr_low;
496 uint32_t reserved2[6];
520 uint32_t firmware_revision;
521 uint32_t bootup_sclk_in10khz;
522 uint32_t bootup_mclk_in10khz;
523 uint32_t firmware_capability; // enum atombios_firmware_capability
524 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
525 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
533 uint32_t mc_baseaddr_high;
534 uint32_t mc_baseaddr_low;
541 uint32_t zfbstartaddrin16mb;
542 uint32_t reserved2[3];
548 uint32_t firmware_revision;
549 uint32_t bootup_sclk_in10khz;
550 uint32_t bootup_mclk_in10khz;
551 uint32_t firmware_capability; // enum atombios_firmware_capability
552 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
553 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
561 uint32_t mc_baseaddr_high;
562 uint32_t mc_baseaddr_low;
569 uint32_t zfbstartaddrin16mb;
570 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
571 uint32_t reserved2[2];
576 uint32_t firmware_revision;
577 uint32_t bootup_sclk_in10khz;
578 uint32_t bootup_mclk_in10khz;
579 uint32_t firmware_capability; // enum atombios_firmware_capability
580 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
581 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
589 uint32_t mc_baseaddr_high;
590 uint32_t mc_baseaddr_low;
597 uint32_t zfbstartaddrin16mb;
598 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
599 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
606 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
607 uint32_t pspbl_init_done_reg_addr;
608 uint32_t pspbl_init_done_value;
609 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done
610 uint32_t reserved[2];
615 uint32_t firmware_revision;
616 uint32_t bootup_clk_reserved[2];
617 uint32_t firmware_capability; // enum atombios_firmware_capability
618 uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */
619 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
620 uint32_t bootup_voltage_reserved[2];
625 uint32_t mc_baseaddr_high;
626 uint32_t mc_baseaddr_low;
631 uint32_t bootup_voltage_reserved1;
632 uint32_t zfb_reserved;
634 uint32_t pplib_pptable_id;
635 uint32_t hw_voltage_reserved[3];
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
638 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
639 uint32_t pspbl_init_reserved[3];
640 uint32_t spi_rom_size; // GPU spi rom size
643 uint32_t reserved[16];
677 uint32_t reserved1[8];
702 uint32_t data_a_reg_index;
786 uint32_t start_address_in_kb;
793 uint32_t fw_region_start_address_in_kb;
796 uint32_t driver_region0_start_address_in_kb;
797 uint32_t used_by_driver_region0_in_kb;
798 uint32_t reserved32[7];
852 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.
874 uint32_t encodercaps;
886 uint32_t connectcaps;
1062 uint32_t display_caps;
1063 uint32_t bootup_dispclk_10khz;
1094 uint32_t display_caps;
1095 uint32_t bootup_dispclk_10khz;
1128 uint32_t display_caps;
1129 uint32_t bootup_dispclk_10khz;
1161 uint32_t display_caps;
1162 uint32_t bootup_dispclk_10khz;
1189 uint32_t dispclk_pll_vco_freq;
1190 uint32_t dp_ref_clk_freq;
1191 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1192 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1193 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1196 uint32_t reserved3[3];
1201 uint32_t aux_dphy_rx_control0_val;
1202 uint32_t aux_dphy_tx_control_val;
1203 uint32_t aux_dphy_rx_control1_val;
1204 uint32_t dc_gpio_aux_ctrl_0_val;
1205 uint32_t dc_gpio_aux_ctrl_1_val;
1206 uint32_t dc_gpio_aux_ctrl_2_val;
1207 uint32_t dc_gpio_aux_ctrl_3_val;
1208 uint32_t dc_gpio_aux_ctrl_4_val;
1209 uint32_t dc_gpio_aux_ctrl_5_val;
1210 uint32_t reserved[23];
1228 uint32_t display_caps;
1229 uint32_t bootup_dispclk_10khz;
1260 uint32_t dispclk_pll_vco_freq;
1261 uint32_t dp_ref_clk_freq;
1263 uint32_t max_mclk_chg_lat;
1265 uint32_t max_sr_exit_lat;
1267 uint32_t max_sr_enter_exit_lat;
1270 uint32_t aux_dphy_rx_control0_val;
1271 uint32_t aux_dphy_tx_control_val;
1272 uint32_t aux_dphy_rx_control1_val;
1273 uint32_t dc_gpio_aux_ctrl_0_val;
1274 uint32_t dc_gpio_aux_ctrl_1_val;
1275 uint32_t dc_gpio_aux_ctrl_2_val;
1276 uint32_t dc_gpio_aux_ctrl_3_val;
1277 uint32_t dc_gpio_aux_ctrl_4_val;
1278 uint32_t dc_gpio_aux_ctrl_5_val;
1279 uint32_t reserved[26];
1333 uint32_t param;
1356 uint32_t versionCode;
1360 uint32_t crc_val; // CRC
1366 uint32_t max_symclk_in10khz;
1412 uint32_t max_symclk_in10khz;
1455 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1456 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1457 uint32_t system_config;
1458 uint32_t cpucapinfo;
1498 uint32_t reserved[66];
1504 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1505 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1506 uint32_t system_config;
1507 uint32_t cpucapinfo;
1548 uint32_t reserved[63];
1557 uint32_t reserved2;
1564 uint32_t reserved4[3];
1570 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1571 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1572 uint32_t system_config;
1573 uint32_t cpucapinfo;
1585 uint32_t reserved3[8];
1591 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1597 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1602 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1603 uint32_t reserved7[32];
1612 uint32_t reserved2;
1613 uint32_t speed_upto;
1626 uint32_t reserved4;
1627 uint32_t reserved5;
1628 uint32_t reserved6;
1639 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1640 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1641 uint32_t system_config;
1642 uint32_t cpucapinfo;
1654 uint32_t reserved3[8];
1657 uint32_t reserved4[189];
1730 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1751 uint32_t regaddr_cp_dma_src_addr;
1752 uint32_t regaddr_cp_dma_src_addr_hi;
1753 uint32_t regaddr_cp_dma_dst_addr;
1754 uint32_t regaddr_cp_dma_dst_addr_hi;
1755 uint32_t regaddr_cp_dma_command;
1756 uint32_t regaddr_cp_status;
1757 uint32_t regaddr_rlc_gpu_clock_32;
1758 uint32_t rlc_gpu_timer_refclk;
1771 uint32_t regaddr_cp_dma_src_addr;
1772 uint32_t regaddr_cp_dma_src_addr_hi;
1773 uint32_t regaddr_cp_dma_dst_addr;
1774 uint32_t regaddr_cp_dma_dst_addr_hi;
1775 uint32_t regaddr_cp_dma_command;
1776 uint32_t regaddr_cp_status;
1777 uint32_t regaddr_rlc_gpu_clock_32;
1778 uint32_t rlc_gpu_timer_refclk;
1782 uint32_t rm21_sram_vmin_value;
1796 uint32_t regaddr_cp_dma_src_addr;
1797 uint32_t regaddr_cp_dma_src_addr_hi;
1798 uint32_t regaddr_cp_dma_dst_addr;
1799 uint32_t regaddr_cp_dma_dst_addr_hi;
1800 uint32_t regaddr_cp_dma_command;
1801 uint32_t regaddr_cp_status;
1802 uint32_t regaddr_rlc_gpu_clock_32;
1803 uint32_t rlc_gpu_timer_refclk;
1817 uint32_t sram_rm_fuses_val;
1818 uint32_t sram_custom_rm_fuses_val;
1831 uint32_t regaddr_cp_dma_src_addr;
1832 uint32_t regaddr_cp_dma_src_addr_hi;
1833 uint32_t regaddr_cp_dma_dst_addr;
1834 uint32_t regaddr_cp_dma_dst_addr_hi;
1835 uint32_t regaddr_cp_dma_command;
1836 uint32_t regaddr_cp_status;
1837 uint32_t regaddr_rlc_gpu_clock_32;
1838 uint32_t rlc_gpu_timer_refclk;
1852 uint32_t sram_rm_fuses_val;
1853 uint32_t sram_custom_rm_fuses_val;
1857 uint32_t gc_config;
1859 uint32_t reserved2[6];
1872 uint32_t regaddr_lsdma_queue0_rb_rptr;
1873 uint32_t regaddr_lsdma_queue0_rb_rptr_hi;
1874 uint32_t regaddr_lsdma_queue0_rb_wptr;
1875 uint32_t regaddr_lsdma_queue0_rb_wptr_hi;
1876 uint32_t regaddr_lsdma_command;
1877 uint32_t regaddr_lsdma_status;
1878 uint32_t regaddr_golden_tsc_count_lower;
1879 uint32_t golden_tsc_count_lower_refclk;
1884 uint32_t sram_rm_fuses_val;
1885 uint32_t sram_custom_rm_fuses_val;
1886 uint32_t inactive_sa_mask;
1887 uint32_t gc_config;
1890 uint32_t gdfll_as_wait_ctrl_val;
1891 uint32_t gdfll_as_step_ctrl_val;
1892 uint32_t reserved[8];
1911 uint32_t core_refclk_10khz;
1932 uint32_t core_refclk_10khz;
1944 uint32_t gpupll_vco_freq_10khz;
1945 uint32_t bootup_smnclk_10khz;
1946 uint32_t bootup_socclk_10khz;
1947 uint32_t bootup_mp0clk_10khz;
1948 uint32_t bootup_mp1clk_10khz;
1949 uint32_t bootup_lclk_10khz;
1950 uint32_t bootup_dcefclk_10khz;
1951 uint32_t ctf_threshold_override_value;
1952 uint32_t reserved[5];
1965 uint32_t core_refclk_10khz;
1977 uint32_t gpupll_vco_freq_10khz;
1978 uint32_t bootup_smnclk_10khz;
1979 uint32_t bootup_socclk_10khz;
1980 uint32_t bootup_mp0clk_10khz;
1981 uint32_t bootup_mp1clk_10khz;
1982 uint32_t bootup_lclk_10khz;
1983 uint32_t bootup_dcefclk_10khz;
1984 uint32_t ctf_threshold_override_value;
1985 uint32_t syspll3_0_vco_freq_10khz;
1986 uint32_t syspll3_1_vco_freq_10khz;
1987 uint32_t bootup_fclk_10khz;
1988 uint32_t bootup_waflclk_10khz;
1989 uint32_t smu_info_caps;
1992 uint32_t reserved;
2006 uint32_t core_refclk_10khz;
2007 uint32_t syspll0_1_vco_freq_10khz;
2008 uint32_t syspll0_2_vco_freq_10khz;
2012 uint32_t syspll0_0_vco_freq_10khz;
2013 uint32_t bootup_smnclk_10khz;
2014 uint32_t bootup_socclk_10khz;
2015 uint32_t bootup_mp0clk_10khz;
2016 uint32_t bootup_mp1clk_10khz;
2017 uint32_t bootup_lclk_10khz;
2018 uint32_t bootup_dcefclk_10khz;
2019 uint32_t ctf_threshold_override_value;
2020 uint32_t syspll3_0_vco_freq_10khz;
2021 uint32_t syspll3_1_vco_freq_10khz;
2022 uint32_t bootup_fclk_10khz;
2023 uint32_t bootup_waflclk_10khz;
2024 uint32_t smu_info_caps;
2027 uint32_t bootup_dprefclk_10khz;
2028 uint32_t bootup_usbclk_10khz;
2029 uint32_t smb_slave_address;
2030 uint32_t cg_fdo_ctrl0_val;
2031 uint32_t cg_fdo_ctrl1_val;
2032 uint32_t cg_fdo_ctrl2_val;
2033 uint32_t gdfll_as_wait_ctrl_val;
2034 uint32_t gdfll_as_step_ctrl_val;
2035 uint32_t bootup_dtbclk_10khz;
2036 uint32_t fclk_syspll_refclk_10khz;
2037 uint32_t smusvi_svc0_val;
2038 uint32_t smusvi_svc1_val;
2039 uint32_t smusvi_svd0_val;
2040 uint32_t smusvi_svd1_val;
2041 uint32_t smusvi_svt0_val;
2042 uint32_t smusvi_svt1_val;
2043 uint32_t cg_tach_ctrl_val;
2044 uint32_t cg_pump_ctrl1_val;
2045 uint32_t cg_pump_tach_ctrl_val;
2046 uint32_t thm_ctf_delay_val;
2047 uint32_t thm_thermal_int_ctrl_val;
2048 uint32_t thm_tmon_config_val;
2049 uint32_t reserved[16];
2063 uint32_t core_refclk_10khz;
2064 uint32_t syspll0_1_vco_freq_10khz;
2065 uint32_t syspll0_2_vco_freq_10khz;
2069 uint32_t syspll0_0_vco_freq_10khz;
2070 uint32_t bootup_smnclk_10khz;
2071 uint32_t bootup_socclk_10khz;
2072 uint32_t bootup_mp0clk_10khz;
2073 uint32_t bootup_mp1clk_10khz;
2074 uint32_t bootup_lclk_10khz;
2075 uint32_t bootup_dxioclk_10khz;
2076 uint32_t ctf_threshold_override_value;
2077 uint32_t syspll3_0_vco_freq_10khz;
2078 uint32_t syspll3_1_vco_freq_10khz;
2079 uint32_t bootup_fclk_10khz;
2080 uint32_t bootup_waflclk_10khz;
2081 uint32_t smu_info_caps;
2084 uint32_t bootup_gfxavsclk_10khz;
2085 uint32_t bootup_mpioclk_10khz;
2086 uint32_t smb_slave_address;
2087 uint32_t cg_fdo_ctrl0_val;
2088 uint32_t cg_fdo_ctrl1_val;
2089 uint32_t cg_fdo_ctrl2_val;
2090 uint32_t gdfll_as_wait_ctrl_val;
2091 uint32_t gdfll_as_step_ctrl_val;
2092 uint32_t reserved_clk;
2093 uint32_t fclk_syspll_refclk_10khz;
2094 uint32_t smusvi_svc0_val;
2095 uint32_t smusvi_svc1_val;
2096 uint32_t smusvi_svd0_val;
2097 uint32_t smusvi_svd1_val;
2098 uint32_t smusvi_svt0_val;
2099 uint32_t smusvi_svt1_val;
2100 uint32_t cg_tach_ctrl_val;
2101 uint32_t cg_pump_ctrl1_val;
2102 uint32_t cg_pump_tach_ctrl_val;
2103 uint32_t thm_ctf_delay_val;
2104 uint32_t thm_thermal_int_ctrl_val;
2105 uint32_t thm_tmon_config_val;
2106 uint32_t bootup_vclk_10khz;
2107 uint32_t bootup_dclk_10khz;
2108 uint32_t smu_gpiopad_pu_en_val;
2109 uint32_t smu_gpiopad_pd_en_val;
2110 uint32_t reserved[12];
2115 uint32_t bootup_gfxclk_bypass_10khz;
2116 uint32_t bootup_usrclk_10khz;
2117 uint32_t bootup_csrclk_10khz;
2118 uint32_t core_refclk_10khz;
2119 uint32_t syspll1_vco_freq_10khz;
2120 uint32_t syspll2_vco_freq_10khz;
2124 uint32_t syspll0_vco_freq_10khz;
2125 uint32_t bootup_smnclk_10khz;
2126 uint32_t bootup_socclk_10khz;
2127 uint32_t bootup_mp0clk_10khz;
2128 uint32_t bootup_mp1clk_10khz;
2129 uint32_t bootup_lclk_10khz;
2130 uint32_t bootup_dcefclk_10khz;
2131 uint32_t ctf_threshold_override_value;
2132 uint32_t syspll3_vco_freq_10khz;
2133 uint32_t mm_syspll_vco_freq_10khz;
2134 uint32_t bootup_fclk_10khz;
2135 uint32_t bootup_waflclk_10khz;
2136 uint32_t smu_info_caps;
2139 uint32_t bootup_dprefclk_10khz;
2140 uint32_t bootup_usbclk_10khz;
2141 uint32_t smb_slave_address;
2142 uint32_t cg_fdo_ctrl0_val;
2143 uint32_t cg_fdo_ctrl1_val;
2144 uint32_t cg_fdo_ctrl2_val;
2145 uint32_t gdfll_as_wait_ctrl_val;
2146 uint32_t gdfll_as_step_ctrl_val;
2147 uint32_t bootup_dtbclk_10khz;
2148 uint32_t fclk_syspll_refclk_10khz;
2149 uint32_t smusvi_svc0_val;
2150 uint32_t smusvi_svc1_val;
2151 uint32_t smusvi_svd0_val;
2152 uint32_t smusvi_svd1_val;
2153 uint32_t smusvi_svt0_val;
2154 uint32_t smusvi_svt1_val;
2155 uint32_t cg_tach_ctrl_val;
2156 uint32_t cg_pump_ctrl1_val;
2157 uint32_t cg_pump_tach_ctrl_val;
2158 uint32_t thm_ctf_delay_val;
2159 uint32_t thm_thermal_int_ctrl_val;
2160 uint32_t thm_tmon_config_val;
2161 uint32_t smbus_timing_cntrl0_val;
2162 uint32_t smbus_timing_cntrl1_val;
2163 uint32_t smbus_timing_cntrl2_val;
2164 uint32_t pwr_disp_timer_global_control_val;
2165 uint32_t bootup_mpioclk_10khz;
2166 uint32_t bootup_dclk0_10khz;
2167 uint32_t bootup_vclk0_10khz;
2168 uint32_t bootup_dclk1_10khz;
2169 uint32_t bootup_vclk1_10khz;
2170 uint32_t bootup_baco400clk_10khz;
2171 uint32_t bootup_baco1200clk_bypass_10khz;
2172 uint32_t bootup_baco700clk_bypass_10khz;
2173 uint32_t reserved[16];
2261 uint32_t boardreserved[9];
2347 uint32_t boardreserved[10];
2351 uint32_t enabled;
2352 uint32_t slaveaddress;
2353 uint32_t controllerport;
2354 uint32_t controllername;
2355 uint32_t thermalthrottler;
2356 uint32_t i2cprotocol;
2357 uint32_t i2cspeed;
2363 uint32_t i2c_padding[3];
2435 uint32_t boardreserved[10];
2477 uint32_t SlaveAddress;
2563 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2565 uint32_t BoardReserved[9];
2573 uint32_t i2c_padding[3]; // old i2c control are moved to new area
2635 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2652 uint32_t boardreserved[10];
2734 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2754 uint32_t BoardReserved[5];
2774 //uint32_t GamingClk[6];
2812 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2858 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2876 uint32_t BoardReserved[16];
2903 uint32_t BoardVoltageCoeffA; // decode by /1000
2904 uint32_t BoardVoltageCoeffB; // decode by /1000
2930 uint32_t reserved[16];
2941 uint32_t maxvddc;
2942 uint32_t minvddc;
2943 uint32_t avfs_meannsigma_acontant0;
2944 uint32_t avfs_meannsigma_acontant1;
2945 uint32_t avfs_meannsigma_acontant2;
2949 uint32_t gb_vdroop_table_cksoff_a0;
2950 uint32_t gb_vdroop_table_cksoff_a1;
2951 uint32_t gb_vdroop_table_cksoff_a2;
2952 uint32_t gb_vdroop_table_ckson_a0;
2953 uint32_t gb_vdroop_table_ckson_a1;
2954 uint32_t gb_vdroop_table_ckson_a2;
2955 uint32_t avfsgb_fuse_table_cksoff_m1;
2956 uint32_t avfsgb_fuse_table_cksoff_m2;
2957 uint32_t avfsgb_fuse_table_cksoff_b;
2958 uint32_t avfsgb_fuse_table_ckson_m1;
2959 uint32_t avfsgb_fuse_table_ckson_m2;
2960 uint32_t avfsgb_fuse_table_ckson_b;
2969 uint32_t dispclk2gfxclk_a;
2970 uint32_t dispclk2gfxclk_b;
2971 uint32_t dispclk2gfxclk_c;
2972 uint32_t pixclk2gfxclk_a;
2973 uint32_t pixclk2gfxclk_b;
2974 uint32_t pixclk2gfxclk_c;
2975 uint32_t dcefclk2gfxclk_a;
2976 uint32_t dcefclk2gfxclk_b;
2977 uint32_t dcefclk2gfxclk_c;
2978 uint32_t phyclk2gfxclk_a;
2979 uint32_t phyclk2gfxclk_b;
2980 uint32_t phyclk2gfxclk_c;
2985 uint32_t maxvddc;
2986 uint32_t minvddc;
2987 uint32_t avfs_meannsigma_acontant0;
2988 uint32_t avfs_meannsigma_acontant1;
2989 uint32_t avfs_meannsigma_acontant2;
2993 uint32_t gb_vdroop_table_cksoff_a0;
2994 uint32_t gb_vdroop_table_cksoff_a1;
2995 uint32_t gb_vdroop_table_cksoff_a2;
2996 uint32_t gb_vdroop_table_ckson_a0;
2997 uint32_t gb_vdroop_table_ckson_a1;
2998 uint32_t gb_vdroop_table_ckson_a2;
2999 uint32_t avfsgb_fuse_table_cksoff_m1;
3000 uint32_t avfsgb_fuse_table_cksoff_m2;
3001 uint32_t avfsgb_fuse_table_cksoff_b;
3002 uint32_t avfsgb_fuse_table_ckson_m1;
3003 uint32_t avfsgb_fuse_table_ckson_m2;
3004 uint32_t avfsgb_fuse_table_ckson_b;
3013 uint32_t dispclk2gfxclk_a;
3014 uint32_t dispclk2gfxclk_b;
3015 uint32_t dispclk2gfxclk_c;
3016 uint32_t pixclk2gfxclk_a;
3017 uint32_t pixclk2gfxclk_b;
3018 uint32_t pixclk2gfxclk_c;
3019 uint32_t dcefclk2gfxclk_a;
3020 uint32_t dcefclk2gfxclk_b;
3021 uint32_t dcefclk2gfxclk_c;
3022 uint32_t phyclk2gfxclk_a;
3023 uint32_t phyclk2gfxclk_b;
3024 uint32_t phyclk2gfxclk_c;
3025 uint32_t acg_gb_vdroop_table_a0;
3026 uint32_t acg_gb_vdroop_table_a1;
3027 uint32_t acg_gb_vdroop_table_a2;
3028 uint32_t acg_avfsgb_fuse_table_m1;
3029 uint32_t acg_avfsgb_fuse_table_m2;
3030 uint32_t acg_avfsgb_fuse_table_b;
3033 uint32_t acg_dispclk2gfxclk_a;
3034 uint32_t acg_dispclk2gfxclk_b;
3035 uint32_t acg_dispclk2gfxclk_c;
3036 uint32_t acg_pixclk2gfxclk_a;
3037 uint32_t acg_pixclk2gfxclk_b;
3038 uint32_t acg_pixclk2gfxclk_c;
3039 uint32_t acg_dcefclk2gfxclk_a;
3040 uint32_t acg_dcefclk2gfxclk_b;
3041 uint32_t acg_dcefclk2gfxclk_c;
3042 uint32_t acg_phyclk2gfxclk_a;
3043 uint32_t acg_phyclk2gfxclk_b;
3044 uint32_t acg_phyclk2gfxclk_c;
3063 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
3064 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
3076 uint32_t ucode_version;
3077 uint32_t ucode_rom_startaddr;
3078 uint32_t ucode_length;
3087 uint32_t mem_refclk_10khz;
3103 uint32_t ucode_version;
3104 uint32_t ucode_rom_startaddr;
3105 uint32_t ucode_length;
3114 uint32_t mem_refclk_10khz;
3115 uint32_t pstate_uclk_10khz[4];
3123 uint32_t ucode_reserved;
3124 uint32_t ucode_rom_startaddr;
3125 uint32_t ucode_length;
3134 uint32_t mem_refclk_10khz;
3135 uint32_t pstate_uclk_10khz[4];
3138 uint32_t umc_config1;
3139 uint32_t bist_data_startaddr;
3140 uint32_t reserved[2];
3154 uint32_t ucode_reserved[5];
3159 uint32_t mem_refclk_10khz;
3160 uint32_t clk_reserved[4];
3161 uint32_t golden_reserved;
3162 uint32_t umc_config1;
3163 uint32_t reserved[2];
3177 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3178 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3179 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3227 uint32_t dram_size_per_ch;
3228 uint32_t reserved[3];
3249 uint32_t channel_enable;
3250 uint32_t channel1_enable;
3251 uint32_t feature_enable;
3252 uint32_t feature1_enable;
3253 uint32_t hardcode_mem_size;
3254 uint32_t reserved4[4];
3259 uint32_t umc_register_addr:24;
3260 uint32_t umc_reg_type_ind:1;
3261 uint32_t umc_reg_rsvd:7;
3272 uint32_t u32umc_reg_addr;
3276 uint32_t memclockrange:24;
3277 uint32_t mem_blk_id:8;
3283 uint32_t u32umc_id_access;
3288 uint32_t u32umc_reg_data[1];
3300 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3301 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3302 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3342 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3343 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3368 uint32_t u32umc_id_access;
3408 uint32_t tXSH;
3432 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap
3433 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0
3434 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1
3435 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2
3436 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0
3437 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1
3438 uint32_t phy_dram; //mmUMC_PHY_DRAM
3442 uint32_t table_size;
3531 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
3542 uint32_t gpio_mask_val; // GPIO Mask value
3593 uint32_t sclkfreqin10khz:24;
3594 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
3599 uint32_t mclkfreqin10khz:24;
3600 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
3612 uint32_t reserved[16];
3637 uint32_t sclkfreqin10khz:24;
3638 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3639 uint32_t reserved[10];
3645 uint32_t reserved[10];
3663 uint32_t sclk_10khz; // current engine speed in 10KHz unit
3664 uint32_t reserved;
3674 uint32_t mclkfreqin10khz:24;
3675 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3676 uint32_t reserved[10];
3682 uint32_t reserved[10];
3693 uint32_t mclk_10khz; // current engine speed in 10KHz unit
3694 uint32_t reserved;
3723 uint32_t reserved[10];
3743 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3744 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
3745 uint32_t reserved[5];
3751 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3752 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
3753 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3754 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3758 uint32_t reserved1[2];
3780 uint32_t efusevalue;
3910 uint32_t smu_clock_freq_hz;
3911 uint32_t syspllvcofreq_10khz;
3912 uint32_t sysspllrefclk_10khz;
3934 uint32_t mclk_10khz:24; //Input= target mclk
3935 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3936 uint32_t reserved;
3942 uint32_t sclk_10khz:24; //Input= target mclk
3943 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3944 uint32_t mclk_10khz;
3945 uint32_t reserved;
3974 uint32_t reserved[5];
3986 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
3996 uint32_t reserved2;
4033 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
4072 uint32_t ulReserved[2];
4084 uint32_t reserved1;
4117 uint32_t ulReserved[4];
4257 uint32_t pclk_10khz; // Pixel Clock in 10Khz
4281 uint32_t reserved2[2];
4289 uint32_t reserved2[2];
4314 uint32_t symclk_10khz; // Symbol Clock in 10Khz
4319 uint32_t reserved1;
4325 uint32_t reserved[4];
4435 uint32_t reserved[2];
4447 uint32_t signature;
4448 uint32_t tableLength; //Length
4453 uint32_t oemRevision;
4454 uint32_t creatorId;
4455 uint32_t creatorRevision;
4461 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
4462 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
4463 uint32_t reserved[4]; //0x3C
4467 uint32_t pcibus; //0x4C
4468 uint32_t pcidevice; //0x50
4469 uint32_t pcifunction; //0x54
4474 uint32_t revision; //0x60
4475 uint32_t imagelength; //0x64