Lines Matching refs:xa
51 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
118 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
186 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
243 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
319 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
364 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
397 #define SDMA0_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
465 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
520 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
577 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
656 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
820 #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
863 #define SDMA0_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
977 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1176 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1370 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1564 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1758 #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1952 #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2146 #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2340 #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2534 #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2728 #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2859 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
2926 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
2994 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
3051 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
3136 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
3169 #define SDMA1_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
3237 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
3292 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
3349 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
3428 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
3592 #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
3635 #define SDMA1_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
3749 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
3948 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4142 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4336 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4530 #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4724 #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
4918 #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5112 #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5306 #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5500 #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
5631 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
5698 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
5766 #define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa
5823 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
5908 #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
5941 #define SDMA2_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
6009 #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
6064 #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
6121 #define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
6200 #define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
6364 #define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
6407 #define SDMA2_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
6521 #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
6720 #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
6914 #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
7108 #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
7302 #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
7496 #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
7690 #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
7884 #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
8078 #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
8272 #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
8403 #define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
8470 #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
8538 #define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa
8595 #define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
8680 #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
8713 #define SDMA3_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
8781 #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
8836 #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
8893 #define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
8972 #define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
9136 #define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
9179 #define SDMA3_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
9293 #define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
9492 #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
9686 #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
9880 #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
10074 #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
10268 #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
10462 #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
10656 #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
10850 #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
11044 #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
11175 #define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
11242 #define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
11310 #define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa
11367 #define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
11452 #define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
11485 #define SDMA4_EDC_COUNTER2__SDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
11553 #define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
11608 #define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
11665 #define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
11744 #define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
11908 #define SDMA4_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
11951 #define SDMA4_RAS_STATUS__F32_DATA_NACK_GEN_ERR__SHIFT 0xa
12065 #define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
12264 #define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
12458 #define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
12652 #define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
12846 #define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
13040 #define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
13234 #define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
13428 #define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
13622 #define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
13816 #define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa