resource/dcn351/dcn351_resource.c

121 #define SRI(reg_name, block, id)\
122 	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 					reg ## block ## id ## _ ## reg_name
125 #define SRI_ARR(reg_name, block, id)\
126 	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 		reg ## block ## id ## _ ## reg_name
132 #define SRI_ARR_I2C(reg_name, block, id)\
133 	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 		reg ## block ## id ## _ ## reg_name
136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
137 	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 		reg ## block ## id ## _ ## reg_name
140 #define SRI2(reg_name, block, id)\
144 #define SRI2_ARR(reg_name, block, id)\
148 #define SRIR(var_name, reg_name, block, id)\
149 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 					reg ## block ## id ## _ ## reg_name
152 #define SRII(reg_name, block, id)\
153 	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 					reg ## block ## id ## _ ## reg_name
156 #define SRII_ARR_2(reg_name, block, id, inst)\
157 	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 		reg ## block ## id ## _ ## reg_name
160 #define SRII_MPC_RMU(reg_name, block, id)\
161 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 					reg ## block ## id ## _ ## reg_name
164 #define SRII_DWB(reg_name, temp_name, block, id)\
165 	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
166 		reg ## block ## id ## _ ## temp_name
168 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
171 #define DCCG_SRII(reg_name, block, id)\
172 	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 		reg ## block ## id ## _ ## reg_name
175 #define VUPDATE_SRII(reg_name, block, id)\
176 	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
177 		reg ## reg_name ## _ ## block ## id
1252 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1300 	/* Mapping of VPG register blocks to HPO DP block instance:
1308 	/* Mapping of APG register blocks to HPO DP block instance:
1316 	/* allocate HPO stream encoder and create VPG sub-block */