resource/dcn316/dcn316_resource.c

152 #define SRI(reg_name, block, id)\
153 	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 					reg ## block ## id ## _ ## reg_name
156 #define SRI2(reg_name, block, id)\
160 #define SRIR(var_name, reg_name, block, id)\
161 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 					reg ## block ## id ## _ ## reg_name
164 #define SRII(reg_name, block, id)\
165 	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 					reg ## block ## id ## _ ## reg_name
168 #define SRII_MPC_RMU(reg_name, block, id)\
169 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 					reg ## block ## id ## _ ## reg_name
172 #define SRII_DWB(reg_name, temp_name, block, id)\
173 	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
174 					reg ## block ## id ## _ ## temp_name
176 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
179 #define DCCG_SRII(reg_name, block, id)\
180 	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 					reg ## block ## id ## _ ## reg_name
183 #define VUPDATE_SRII(reg_name, block, id)\
184 	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
185 					reg ## reg_name ## _ ## block ## id
1223 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1264 	/* Mapping of VPG register blocks to HPO DP block instance:
1272 	/* Mapping of APG register blocks to HPO DP block instance:
1280 	/* allocate HPO stream encoder and create VPG sub-block */