Lines Matching defs:pool

1341 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1345 for (i = 0; i < pool->base.stream_enc_count; i++) {
1346 if (pool->base.stream_enc[i] != NULL) {
1347 if (pool->base.stream_enc[i]->vpg != NULL) {
1348 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1349 pool->base.stream_enc[i]->vpg = NULL;
1351 if (pool->base.stream_enc[i]->afmt != NULL) {
1352 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1353 pool->base.stream_enc[i]->afmt = NULL;
1355 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1356 pool->base.stream_enc[i] = NULL;
1360 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1361 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1362 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1363 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1364 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1366 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1367 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1368 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1370 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1371 pool->base.hpo_dp_stream_enc[i] = NULL;
1375 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1376 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1377 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1378 pool->base.hpo_dp_link_enc[i] = NULL;
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1383 if (pool->base.dscs[i] != NULL)
1384 dcn20_dsc_destroy(&pool->base.dscs[i]);
1387 if (pool->base.mpc != NULL) {
1388 kfree(TO_DCN20_MPC(pool->base.mpc));
1389 pool->base.mpc = NULL;
1391 if (pool->base.hubbub != NULL) {
1392 kfree(pool->base.hubbub);
1393 pool->base.hubbub = NULL;
1395 for (i = 0; i < pool->base.pipe_count; i++) {
1396 if (pool->base.dpps[i] != NULL)
1397 dcn31_dpp_destroy(&pool->base.dpps[i]);
1399 if (pool->base.ipps[i] != NULL)
1400 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1402 if (pool->base.hubps[i] != NULL) {
1403 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1404 pool->base.hubps[i] = NULL;
1407 if (pool->base.irqs != NULL) {
1408 dal_irq_service_destroy(&pool->base.irqs);
1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1413 if (pool->base.engines[i] != NULL)
1414 dce110_engine_destroy(&pool->base.engines[i]);
1415 if (pool->base.hw_i2cs[i] != NULL) {
1416 kfree(pool->base.hw_i2cs[i]);
1417 pool->base.hw_i2cs[i] = NULL;
1419 if (pool->base.sw_i2cs[i] != NULL) {
1420 kfree(pool->base.sw_i2cs[i]);
1421 pool->base.sw_i2cs[i] = NULL;
1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1426 if (pool->base.opps[i] != NULL)
1427 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1431 if (pool->base.timing_generators[i] != NULL) {
1432 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1433 pool->base.timing_generators[i] = NULL;
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1438 if (pool->base.dwbc[i] != NULL) {
1439 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1440 pool->base.dwbc[i] = NULL;
1442 if (pool->base.mcif_wb[i] != NULL) {
1443 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1444 pool->base.mcif_wb[i] = NULL;
1448 for (i = 0; i < pool->base.audio_count; i++) {
1449 if (pool->base.audios[i])
1450 dce_aud_destroy(&pool->base.audios[i]);
1453 for (i = 0; i < pool->base.clk_src_count; i++) {
1454 if (pool->base.clock_sources[i] != NULL) {
1455 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1456 pool->base.clock_sources[i] = NULL;
1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1461 if (pool->base.mpc_lut[i] != NULL) {
1462 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1463 pool->base.mpc_lut[i] = NULL;
1465 if (pool->base.mpc_shaper[i] != NULL) {
1466 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1467 pool->base.mpc_shaper[i] = NULL;
1471 if (pool->base.dp_clock_source != NULL) {
1472 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1473 pool->base.dp_clock_source = NULL;
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1477 if (pool->base.multiple_abms[i] != NULL)
1478 dce_abm_destroy(&pool->base.multiple_abms[i]);
1481 if (pool->base.psr != NULL)
1482 dmub_psr_destroy(&pool->base.psr);
1484 if (pool->base.dccg != NULL)
1485 dcn_dccg_destroy(&pool->base.dccg);
1507 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1510 uint32_t pipe_count = pool->res_cap->num_dwb;
1527 pool->dwbc[i] = &dwbc30->base;
1532 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1535 uint32_t pipe_count = pool->res_cap->num_dwb;
1552 pool->mcif_wb[i] = &mcif_wb30->base;
1572 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1574 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1578 *pool = NULL;
1728 struct dcn316_resource_pool *pool)
1736 pool->base.res_cap = &res_cap_dcn31;
1738 pool->base.funcs = &dcn316_res_pool_funcs;
1743 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1744 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1745 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1791 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1828 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1832 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1836 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1840 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1844 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1849 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1852 pool->base.dp_clock_source =
1857 for (i = 0; i < pool->base.clk_src_count; i++) {
1858 if (pool->base.clock_sources[i] == NULL) {
1866 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1867 if (pool->base.dccg == NULL) {
1875 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1876 if (!pool->base.irqs)
1880 pool->base.hubbub = dcn31_hubbub_create(ctx);
1881 if (pool->base.hubbub == NULL) {
1888 for (i = 0; i < pool->base.pipe_count; i++) {
1889 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1890 if (pool->base.hubps[i] == NULL) {
1897 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1898 if (pool->base.dpps[i] == NULL) {
1906 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1907 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1908 if (pool->base.opps[i] == NULL) {
1916 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1917 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1919 if (pool->base.timing_generators[i] == NULL) {
1925 pool->base.timing_generator_count = i;
1928 pool->base.psr = dmub_psr_create(ctx);
1929 if (pool->base.psr == NULL) {
1936 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1937 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1941 if (pool->base.multiple_abms[i] == NULL) {
1949 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1950 if (pool->base.mpc == NULL) {
1956 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1957 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1958 if (pool->base.dscs[i] == NULL) {
1966 if (!dcn31_dwbc_create(ctx, &pool->base)) {
1972 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1979 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1980 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1981 if (pool->base.engines[i] == NULL) {
1987 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1988 if (pool->base.hw_i2cs[i] == NULL) {
1994 pool->base.sw_i2cs[i] = NULL;
1998 if (!resource_construct(num_virtual_links, dc, &pool->base,
2005 dc->caps.max_planes = pool->base.pipe_count;
2018 dcn316_resource_destruct(pool);
2027 struct dcn316_resource_pool *pool =
2030 if (!pool)
2033 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2034 return &pool->base;
2037 kfree(pool);