resource/dcn316/dcn316_resource.c

28 #include "dc.h"
957 					ctx->dc->caps.extended_aux_timeout_support);
1112 	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1612 	struct dc *dc, struct dc_state *context,
1622 	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1625 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1674 	dc->config.enable_4to1MPC = false;
1675 	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1678 			dc->config.enable_4to1MPC = true;
1727 	struct dc *dc,
1731 	struct dc_context *ctx = dc->ctx;
1746 	dc->caps.max_downscale_ratio = 600;
1747 	dc->caps.i2c_speed_in_khz = 100;
1748 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1749 	dc->caps.max_cursor_size = 256;
1750 	dc->caps.min_horizontal_blanking_period = 80;
1751 	dc->caps.dmdata_alloc_size = 2048;
1752 	dc->caps.max_slave_planes = 2;
1753 	dc->caps.max_slave_yuv_planes = 2;
1754 	dc->caps.max_slave_rgb_planes = 2;
1755 	dc->caps.post_blend_color_processing = true;
1756 	dc->caps.force_dp_tps4_for_cp2520 = true;
1757 	if (dc->config.forceHBR2CP2520)
1758 		dc->caps.force_dp_tps4_for_cp2520 = false;
1759 	dc->caps.dp_hpo = true;
1760 	dc->caps.dp_hdmi21_pcon_support = true;
1761 	dc->caps.edp_dsc_support = true;
1762 	dc->caps.extended_aux_timeout_support = true;
1763 	dc->caps.dmcub_support = true;
1764 	dc->caps.is_apu = true;
1767 	dc->caps.color.dpp.dcn_arch = 1;
1768 	dc->caps.color.dpp.input_lut_shared = 0;
1769 	dc->caps.color.dpp.icsc = 1;
1770 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1771 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1772 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1773 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1774 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1775 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1776 	dc->caps.color.dpp.post_csc = 1;
1777 	dc->caps.color.dpp.gamma_corr = 1;
1778 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1780 	dc->caps.color.dpp.hw_3d_lut = 1;
1781 	dc->caps.color.dpp.ogam_ram = 1;
1783 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1784 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1785 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1786 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1787 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1788 	dc->caps.color.dpp.ocsc = 0;
1790 	dc->caps.color.mpc.gamut_remap = 1;
1791 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1792 	dc->caps.color.mpc.ogam_ram = 1;
1793 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1794 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1795 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1796 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1797 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1798 	dc->caps.color.mpc.ocsc = 1;
1807 			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1812 			dc->caps.vbios_lttpr_aware = true;
1816 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1817 		dc->debug = debug_defaults_drv;
1820 	if (dc->vm_helper)
1821 		vm_helper_init(dc->vm_helper, 16);
1874 	init_data.ctx = dc->ctx;
1998 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2003 	dcn31_hw_sequencer_construct(dc);
2005 	dc->caps.max_planes =  pool->base.pipe_count;
2007 	for (i = 0; i < dc->caps.max_planes; ++i)
2008 		dc->caps.planes[i] = plane_cap;
2010 	dc->cap_funcs = cap_funcs;
2012 	dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2025 		struct dc *dc)
2033 	if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))