resource/dcn315/dcn315_resource.c

165 #define SRI(reg_name, block, id)\
166 	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 					reg ## block ## id ## _ ## reg_name
169 #define SRI2(reg_name, block, id)\
173 #define SRIR(var_name, reg_name, block, id)\
174 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 					reg ## block ## id ## _ ## reg_name
177 #define SRII(reg_name, block, id)\
178 	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 					reg ## block ## id ## _ ## reg_name
181 #define SRII_MPC_RMU(reg_name, block, id)\
182 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 					reg ## block ## id ## _ ## reg_name
185 #define SRII_DWB(reg_name, temp_name, block, id)\
186 	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
187 					reg ## block ## id ## _ ## temp_name
189 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
192 #define DCCG_SRII(reg_name, block, id)\
193 	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
194 					reg ## block ## id ## _ ## reg_name
196 #define VUPDATE_SRII(reg_name, block, id)\
197 	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
198 					reg ## reg_name ## _ ## block ## id
1228 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1268 	/* Mapping of VPG register blocks to HPO DP block instance:
1276 	/* Mapping of APG register blocks to HPO DP block instance:
1284 	/* allocate HPO stream encoder and create VPG sub-block */