Lines Matching defs:dc

28 #include "dc.h"
962 ctx->dc->caps.extended_aux_timeout_support);
1117 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1631 static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
1642 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1662 struct dc *dc, struct dc_state *context,
1671 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
1674 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1677 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1706 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
1743 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
1756 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
1787 dc->config.enable_4to1MPC = false;
1788 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1791 dc->config.enable_4to1MPC = true;
1796 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
1843 struct dc *dc,
1847 struct dc_context *ctx = dc->ctx;
1862 dc->caps.max_downscale_ratio = 600;
1863 dc->caps.i2c_speed_in_khz = 100;
1864 dc->caps.i2c_speed_in_khz_hdcp = 100;
1865 dc->caps.max_cursor_size = 256;
1866 dc->caps.min_horizontal_blanking_period = 80;
1867 dc->caps.dmdata_alloc_size = 2048;
1868 dc->caps.max_slave_planes = 2;
1869 dc->caps.max_slave_yuv_planes = 2;
1870 dc->caps.max_slave_rgb_planes = 2;
1871 dc->caps.post_blend_color_processing = true;
1872 dc->caps.force_dp_tps4_for_cp2520 = true;
1873 if (dc->config.forceHBR2CP2520)
1874 dc->caps.force_dp_tps4_for_cp2520 = false;
1875 dc->caps.dp_hpo = true;
1876 dc->caps.dp_hdmi21_pcon_support = true;
1877 dc->caps.edp_dsc_support = true;
1878 dc->caps.extended_aux_timeout_support = true;
1879 dc->caps.dmcub_support = true;
1880 dc->caps.is_apu = true;
1883 dc->caps.color.dpp.dcn_arch = 1;
1884 dc->caps.color.dpp.input_lut_shared = 0;
1885 dc->caps.color.dpp.icsc = 1;
1886 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1887 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1888 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1889 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1890 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1891 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1892 dc->caps.color.dpp.post_csc = 1;
1893 dc->caps.color.dpp.gamma_corr = 1;
1894 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1896 dc->caps.color.dpp.hw_3d_lut = 1;
1897 dc->caps.color.dpp.ogam_ram = 1;
1899 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1900 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1901 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1902 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1903 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1904 dc->caps.color.dpp.ocsc = 0;
1906 dc->caps.color.mpc.gamut_remap = 1;
1907 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1908 dc->caps.color.mpc.ogam_ram = 1;
1909 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1910 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1911 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1912 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1913 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1914 dc->caps.color.mpc.ocsc = 1;
1923 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1928 dc->caps.vbios_lttpr_aware = true;
1932 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1933 dc->debug = debug_defaults_drv;
1936 if (dc->vm_helper)
1937 vm_helper_init(dc->vm_helper, 16);
1990 init_data.ctx = dc->ctx;
2114 if (!resource_construct(num_virtual_links, dc, &pool->base,
2119 dcn31_hw_sequencer_construct(dc);
2121 dc->caps.max_planes = pool->base.pipe_count;
2123 for (i = 0; i < dc->caps.max_planes; ++i)
2124 dc->caps.planes[i] = plane_cap;
2126 dc->cap_funcs = cap_funcs;
2128 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;
2141 struct dc *dc)
2149 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))