resource/dcn314/dcn314_resource.c

149 #define SRI(reg_name, block, id)\
150 	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 					reg ## block ## id ## _ ## reg_name
153 #define SRI2(reg_name, block, id)\
157 #define SRIR(var_name, reg_name, block, id)\
158 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 					reg ## block ## id ## _ ## reg_name
161 #define SRII(reg_name, block, id)\
162 	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 					reg ## block ## id ## _ ## reg_name
165 #define SRII_MPC_RMU(reg_name, block, id)\
166 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 					reg ## block ## id ## _ ## reg_name
169 #define SRII_DWB(reg_name, temp_name, block, id)\
170 	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
171 					reg ## block ## id ## _ ## temp_name
173 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
176 #define DCCG_SRII(reg_name, block, id)\
177 	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 					reg ## block ## id ## _ ## reg_name
180 #define VUPDATE_SRII(reg_name, block, id)\
181 	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
182 					reg ## reg_name ## _ ## block ## id
213 #define CLK_SRI(reg_name, block, inst)\
214 	.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
215 					reg ## block ## _ ## inst ## _ ## reg_name
1285 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1325 	/* Mapping of VPG register blocks to HPO DP block instance:
1334 	/* Mapping of APG register blocks to HPO DP block instance:
1342 	/* allocate HPO stream encoder and create VPG sub-block */