Lines Matching refs:block
178 #define SRI(reg_name, block, id)\
179 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
181 #define SRI2(reg_name, block, id)\
184 #define SRII(reg_name, block, id)\
185 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 mm ## block ## id ## _ ## reg_name
188 #define DCCG_SRII(reg_name, block, id)\
189 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 mm ## block ## id ## _ ## reg_name
192 #define VUPDATE_SRII(reg_name, block, id)\
193 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
194 mm ## reg_name ## _ ## block ## id
196 #define SRII_DWB(reg_name, temp_name, block, id)\
197 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
198 mm ## block ## id ## _ ## temp_name
200 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
203 #define SRII_MPC_RMU(reg_name, block, id)\
204 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
205 mm ## block ## id ## _ ## reg_name
386 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */