Lines Matching refs:block
120 #define SRI(reg_name, block, id)\
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define SRI2(reg_name, block, id)\
128 #define SRIR(var_name, reg_name, block, id)\
129 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 mm ## block ## id ## _ ## reg_name
132 #define SRII(reg_name, block, id)\
133 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
141 #define SRII_MPC_RMU(reg_name, block, id)\
142 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## reg_name
145 #define SRII_DWB(reg_name, temp_name, block, id)\
146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
147 mm ## block ## id ## _ ## temp_name
149 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
152 #define DCCG_SRII(reg_name, block, id)\
153 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 mm ## block ## id ## _ ## reg_name
156 #define VUPDATE_SRII(reg_name, block, id)\
157 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
158 mm ## reg_name ## _ ## block ## id
189 #define CLK_SRI(reg_name, block, inst)\
190 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
191 mm ## block ## _ ## inst ## _ ## reg_name
991 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */