Lines Matching refs:block
105 #define SRI(reg_name, block, id)\
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 mm ## block ## id ## _ ## reg_name
113 #define SRII(reg_name, block, id)\
114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 mm ## block ## id ## _ ## reg_name
117 #define DCCG_SRII(reg_name, block, id)\
118 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 mm ## block ## id ## _ ## reg_name
121 #define VUPDATE_SRII(reg_name, block, id)\
122 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
123 mm ## reg_name ## _ ## block ## id
1357 /* align to our worst case block width */