resource/dcn21/dcn21_resource.c

30 #include "dc.h"
533 					ctx->dc->caps.extended_aux_timeout_support);
748 		if (pool->base.abm->ctx->dc->config.disable_dmcu)
767 bool dcn21_fast_validate_bw(struct dc *dc,
783 	dcn20_merge_pipes_for_validate(dc, context);
786 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
819 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
821 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
845 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
855 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
858 					dc, &context->res_ctx,
862 			dcn20_build_mapped_resource(dc, context, pipe->stream);
874 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
884 							dc, &context->res_ctx,
887 					dcn20_build_mapped_resource(dc, context, pipe->stream);
890 							&context->res_ctx, dc->res_pool,
903 	if (!dcn20_validate_dsc(dc, context)) {
926 static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
932 	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
937 	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);
1355 	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1385 	struct dc *dc,
1389 	struct dc_context *ctx = dc->ctx;
1408 	dc->caps.max_downscale_ratio = 200;
1409 	dc->caps.i2c_speed_in_khz = 100;
1410 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1411 	dc->caps.max_cursor_size = 256;
1412 	dc->caps.min_horizontal_blanking_period = 80;
1413 	dc->caps.dmdata_alloc_size = 2048;
1415 	dc->caps.max_slave_planes = 1;
1416 	dc->caps.max_slave_yuv_planes = 1;
1417 	dc->caps.max_slave_rgb_planes = 1;
1418 	dc->caps.post_blend_color_processing = true;
1419 	dc->caps.force_dp_tps4_for_cp2520 = true;
1420 	dc->caps.extended_aux_timeout_support = true;
1421 	dc->caps.dmcub_support = true;
1422 	dc->caps.is_apu = true;
1425 	dc->caps.color.dpp.dcn_arch = 1;
1426 	dc->caps.color.dpp.input_lut_shared = 0;
1427 	dc->caps.color.dpp.icsc = 1;
1428 	dc->caps.color.dpp.dgam_ram = 1;
1429 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1430 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1431 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1432 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1433 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1434 	dc->caps.color.dpp.post_csc = 0;
1435 	dc->caps.color.dpp.gamma_corr = 0;
1436 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1438 	dc->caps.color.dpp.hw_3d_lut = 1;
1439 	dc->caps.color.dpp.ogam_ram = 1;
1441 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1442 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1443 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1444 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1445 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1446 	dc->caps.color.dpp.ocsc = 0;
1448 	dc->caps.color.mpc.gamut_remap = 0;
1449 	dc->caps.color.mpc.num_3dluts = 0;
1450 	dc->caps.color.mpc.shared_3d_lut = 0;
1451 	dc->caps.color.mpc.ogam_ram = 1;
1452 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1453 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1454 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1455 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1456 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1457 	dc->caps.color.mpc.ocsc = 1;
1459 	dc->caps.dp_hdmi21_pcon_support = true;
1461 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1462 		dc->debug = debug_defaults_drv;
1465 	if (dc->vm_helper)
1466 		vm_helper_init(dc->vm_helper, 16);
1516 	if (!dc->config.disable_dmcu) {
1527 		dc->debug.dmub_command_table = false;
1530 	if (dc->config.disable_dmcu) {
1540 	if (dc->config.disable_dmcu)
1561 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1563 	init_data.ctx = dc->ctx;
1675 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1679 	dcn21_hw_sequencer_construct(dc);
1681 	dc->caps.max_planes =  pool->base.pipe_count;
1683 	for (i = 0; i < dc->caps.max_planes; ++i)
1684 		dc->caps.planes[i] = plane_cap;
1686 	dc->cap_funcs = cap_funcs;
1699 		struct dc *dc)
1707 	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))