Lines Matching refs:block
255 #define SRI(reg_name, block, id)\
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 mm ## block ## id ## _ ## reg_name
263 #define SRII(reg_name, block, id)\
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
265 mm ## block ## id ## _ ## reg_name
267 #define SRI_IX(reg_name, block, id)\
268 .reg_name = ix ## block ## id ## _ ## reg_name
270 #define DCCG_SRII(reg_name, block, id)\
271 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
272 mm ## block ## id ## _ ## reg_name
274 #define VUPDATE_SRII(reg_name, block, id)\
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
276 mm ## reg_name ## _ ## block ## id