resource/dce80/dce80_resource.c

545 					ctx->dc->caps.extended_aux_timeout_support);
873 	struct dc *dc,
880 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
918 		struct dc *dc,
949 	struct dc *dc,
953 	struct dc_context *ctx = dc->ctx;
968 	dc->caps.max_downscale_ratio = 200;
969 	dc->caps.i2c_speed_in_khz = 40;
970 	dc->caps.i2c_speed_in_khz_hdcp = 40;
971 	dc->caps.max_cursor_size = 128;
972 	dc->caps.min_horizontal_blanking_period = 80;
973 	dc->caps.dual_link_dvi = true;
974 	dc->caps.extended_aux_timeout_support = false;
975 	dc->debug = debug_defaults;
1042 		init_data.ctx = dc->ctx;
1110 	dc->caps.max_planes =  pool->base.pipe_count;
1112 	for (i = 0; i < dc->caps.max_planes; ++i)
1113 		dc->caps.planes[i] = plane_cap;
1115 	dc->caps.disable_dp_clk_share = true;
1117 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1122 	dce80_hw_sequencer_construct(dc);
1133 	struct dc *dc)
1141 	if (dce80_construct(num_virtual_links, dc, pool))
1151 	struct dc *dc,
1155 	struct dc_context *ctx = dc->ctx;
1170 	dc->caps.max_downscale_ratio = 200;
1171 	dc->caps.i2c_speed_in_khz = 40;
1172 	dc->caps.i2c_speed_in_khz_hdcp = 40;
1173 	dc->caps.max_cursor_size = 128;
1174 	dc->caps.min_horizontal_blanking_period = 80;
1175 	dc->caps.is_apu = true;
1242 		init_data.ctx = dc->ctx;
1310 	dc->caps.max_planes =  pool->base.pipe_count;
1312 	for (i = 0; i < dc->caps.max_planes; ++i)
1313 		dc->caps.planes[i] = plane_cap;
1315 	dc->caps.disable_dp_clk_share = true;
1317 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1322 	dce80_hw_sequencer_construct(dc);
1333 	struct dc *dc)
1341 	if (dce81_construct(num_virtual_links, dc, pool))
1351 	struct dc *dc,
1355 	struct dc_context *ctx = dc->ctx;
1370 	dc->caps.max_downscale_ratio = 200;
1371 	dc->caps.i2c_speed_in_khz = 40;
1372 	dc->caps.i2c_speed_in_khz_hdcp = 40;
1373 	dc->caps.max_cursor_size = 128;
1374 	dc->caps.min_horizontal_blanking_period = 80;
1375 	dc->caps.is_apu = true;
1376 	dc->debug = debug_defaults;
1439 		init_data.ctx = dc->ctx;
1507 	dc->caps.max_planes =  pool->base.pipe_count;
1509 	for (i = 0; i < dc->caps.max_planes; ++i)
1510 		dc->caps.planes[i] = plane_cap;
1512 	dc->caps.disable_dp_clk_share = true;
1514 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1519 	dce80_hw_sequencer_construct(dc);
1530 	struct dc *dc)
1538 	if (dce83_construct(num_virtual_links, dc, pool))