resource/dce112/dce112_resource.c

777 static void dce112_resource_destruct(struct dce110_resource_pool *pool)
781 	for (i = 0; i < pool->base.pipe_count; i++) {
782 		if (pool->base.opps[i] != NULL)
783 			dce110_opp_destroy(&pool->base.opps[i]);
785 		if (pool->base.transforms[i] != NULL)
786 			dce112_transform_destroy(&pool->base.transforms[i]);
788 		if (pool->base.ipps[i] != NULL)
789 			dce_ipp_destroy(&pool->base.ipps[i]);
791 		if (pool->base.mis[i] != NULL) {
792 			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
793 			pool->base.mis[i] = NULL;
796 		if (pool->base.timing_generators[i] != NULL) {
797 			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
798 			pool->base.timing_generators[i] = NULL;
802 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
803 		if (pool->base.engines[i] != NULL)
804 			dce110_engine_destroy(&pool->base.engines[i]);
805 		if (pool->base.hw_i2cs[i] != NULL) {
806 			kfree(pool->base.hw_i2cs[i]);
807 			pool->base.hw_i2cs[i] = NULL;
809 		if (pool->base.sw_i2cs[i] != NULL) {
810 			kfree(pool->base.sw_i2cs[i]);
811 			pool->base.sw_i2cs[i] = NULL;
815 	for (i = 0; i < pool->base.stream_enc_count; i++) {
816 		if (pool->base.stream_enc[i] != NULL)
817 			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
820 	for (i = 0; i < pool->base.clk_src_count; i++) {
821 		if (pool->base.clock_sources[i] != NULL) {
822 			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
826 	if (pool->base.dp_clock_source != NULL)
827 		dce112_clock_source_destroy(&pool->base.dp_clock_source);
829 	for (i = 0; i < pool->base.audio_count; i++)	{
830 		if (pool->base.audios[i] != NULL) {
831 			dce_aud_destroy(&pool->base.audios[i]);
835 	if (pool->base.abm != NULL)
836 		dce_abm_destroy(&pool->base.abm);
838 	if (pool->base.dmcu != NULL)
839 		dce_dmcu_destroy(&pool->base.dmcu);
841 	if (pool->base.irqs != NULL) {
842 		dal_irq_service_destroy(&pool->base.irqs);
848 		const struct resource_pool *pool,
853 		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
855 		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
857 		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
859 		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
861 		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
863 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
1042 static void dce112_destroy_resource_pool(struct resource_pool **pool)
1044 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1048 	*pool = NULL;
1223 	struct dce110_resource_pool *pool)
1230 	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1231 	pool->base.funcs = &dce112_res_pool_funcs;
1236 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1237 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1238 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1252 	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1257 	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1262 	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1267 	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1272 	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1277 	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1282 	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1284 	pool->base.dp_clock_source =  dce112_clock_source_create(
1289 	for (i = 0; i < pool->base.clk_src_count; i++) {
1290 		if (pool->base.clock_sources[i] == NULL) {
1297 	pool->base.dmcu = dce_dmcu_create(ctx,
1301 	if (pool->base.dmcu == NULL) {
1307 	pool->base.abm = dce_abm_create(ctx,
1311 	if (pool->base.abm == NULL) {
1320 		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1321 		if (!pool->base.irqs)
1325 	for (i = 0; i < pool->base.pipe_count; i++) {
1326 		pool->base.timing_generators[i] =
1331 		if (pool->base.timing_generators[i] == NULL) {
1337 		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1338 		if (pool->base.mis[i] == NULL) {
1345 		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1346 		if (pool->base.ipps[i] == NULL) {
1353 		pool->base.transforms[i] = dce112_transform_create(ctx, i);
1354 		if (pool->base.transforms[i] == NULL) {
1361 		pool->base.opps[i] = dce112_opp_create(
1364 		if (pool->base.opps[i] == NULL) {
1372 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1373 		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1374 		if (pool->base.engines[i] == NULL) {
1380 		pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1381 		if (pool->base.hw_i2cs[i] == NULL) {
1387 		pool->base.sw_i2cs[i] = NULL;
1390 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1394 	dc->caps.max_planes =  pool->base.pipe_count;
1409 	dce112_resource_destruct(pool);
1417 	struct dce110_resource_pool *pool =
1420 	if (!pool)
1423 	if (dce112_resource_construct(num_virtual_links, dc, pool))
1424 		return &pool->base;
1426 	kfree(pool);