link/protocols/link_dp_training_fixed_vs_pe_retimer.c

52 	uint8_t lane;
54 	/* W/A to read lane settings requested by DPRX */
65 	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
66 		dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET  = (dprx_vs >> (2 * lane)) & 0x3;
67 		dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3;
80 	uint8_t lane = 0;
82 	for (lane = 0; lane < lane_count; lane++) {
84 				dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
86 				dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
106 	uint8_t lane = 0;
128 	/* 1. set link rate, lane count and spread. */
168 			for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
169 				lt_settings->dpcd_lane_settings[lane].raw = 0;
170 				lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
171 				lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
212 	uint8_t lane = 0;
237 	/* Vendor specific: Reset lane settings */
249 	/* 1. set link rate, lane count and spread. */
290 	DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
342 			/* 1. call HWSS to set lane settings */
376 				for (lane = 0; lane < lane_count; lane++) {
378 							lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
380 							lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
402 			/* 4. Read lane status and requested drive
423 			/* 7. same lane settings */
425 			 * so comparing first lane is sufficient
483 			for (lane = 0; lane < lane_count; lane++) {
485 						lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
487 						lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
521 			/* 4. Read lane status and requested