link/protocols/link_dp_training_fixed_vs_pe_retimer.c

103 		struct link_training_settings *lt_settings)
114 	if (lt_settings->cr_pattern_time < 16000)
115 		lt_settings->cr_pattern_time = 16000;
119 	target_rate = get_dpcd_link_rate(&lt_settings->link_settings);
123 		lt_settings->link_settings.link_rate = toggle_rate;
126 		start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);
129 	dpcd_set_link_settings(link, lt_settings);
142 	if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
151 			status = perform_8b_10b_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
160 					lt_settings,
169 				lt_settings->dpcd_lane_settings[lane].raw = 0;
170 				lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
171 				lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
177 		status = perform_8b_10b_clock_recovery_sequence(link, link_res, lt_settings, DPRX);
181 								       lt_settings,
192 	struct link_training_settings *lt_settings)
219 	ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) ==
222 	if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
223 		status = perform_fixed_vs_pe_nontransparent_training_sequence(link, link_res, lt_settings);
251 	downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread);
254 	lt_settings->link_settings.lane_count;
256 	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
260 	if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
271 	rate = get_dpcd_link_rate(&lt_settings->link_settings);
293 		lt_settings->link_settings.link_rate,
295 		lt_settings->link_settings.lane_count,
296 		lt_settings->enhanced_framing,
298 		lt_settings->link_settings.link_spread);
304 	if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) {
325 		enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
346 					lt_settings,
356 						lt_settings,
357 						lt_settings->pattern_for_cr,
378 							lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
380 							lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
391 						lt_settings,
396 			wait_time_microsec = lt_settings->cr_pattern_time;
407 					lt_settings,
420 			if (dp_is_max_vs_reached(lt_settings))
427 			if (lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
433 			/* 8. update VS/PE/PC2 in lt_settings*/
434 			dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
435 					lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
455 		enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
469 		tr_pattern = lt_settings->pattern_for_eq;
478 			dp_set_hw_lane_settings(link, link_res, lt_settings, 0);
485 						lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
487 						lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
504 					lt_settings,
512 				dpcd_set_lane_settings(link, lt_settings, 0);
515 			wait_time_microsec = lt_settings->eq_pattern_time;
526 				lt_settings,
546 			/* 7. update VS/PE/PC2 in lt_settings*/
547 			dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
548 					lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);