link/protocols/link_dp_training_128b_132b.c

74 		struct link_training_settings *lt_settings)
86 	dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, DPRX);
89 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cr);
93 	dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
95 	dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
96 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
97 	dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
98 	dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_eq, DPRX);
104 	dpcd_set_lt_pattern_and_lane_settings(link, lt_settings,
105 			lt_settings->pattern_for_eq, DPRX);
111 		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
113 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
114 				lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
118 		} else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count,
122 		} else if (loop_count >= lt_settings->eq_loop_count_limit) {
127 			dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
128 			dpcd_128b_132b_set_lane_settings(link, lt_settings);
140 		} else if (wait_time >= lt_settings->eq_wait_time_limit) {
146 					lt_settings->eq_pattern_time);
147 			wait_time += lt_settings->eq_pattern_time;
148 			status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
159 		struct link_training_settings *lt_settings)
170 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cds);
175 				lt_settings->cds_pattern_time);
176 		wait_time += lt_settings->cds_pattern_time;
177 		status = dp_get_lane_status_and_lane_adjust(link, lt_settings, dpcd_lane_status,
181 		} else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) &&
187 		} else if (wait_time >= lt_settings->cds_wait_time_limit) {
198 		struct link_training_settings *lt_settings)
207 				&lt_settings->link_settings,
212 	dpcd_set_link_settings(link, lt_settings);
215 		result = dp_perform_128b_132b_channel_eq_done_sequence(link, link_res, lt_settings);
221 		result = dp_perform_128b_132b_cds_done_sequence(link, link_res, lt_settings);
231 		struct link_training_settings *lt_settings)
233 	memset(lt_settings, 0, sizeof(*lt_settings));
235 	lt_settings->link_settings = *link_settings;
237 	lt_settings->link_settings.link_spread = link->dp_ss_off ? LINK_SPREAD_DISABLED :
240 	lt_settings->pattern_for_cr = decide_cr_training_pattern(link_settings);
241 	lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_settings);
242 	lt_settings->eq_pattern_time = 2500;
243 	lt_settings->eq_wait_time_limit = 400000;
244 	lt_settings->eq_loop_count_limit = 20;
245 	lt_settings->pattern_for_cds = DP_128b_132b_TPS2_CDS;
246 	lt_settings->cds_pattern_time = 2500;
247 	lt_settings->cds_wait_time_limit = (dp_parse_lttpr_repeater_count(
249 	lt_settings->disallow_per_lane_settings = true;
250 	lt_settings->lttpr_mode = dp_decide_128b_132b_lttpr_mode(link);
251 	dp_hw_to_dpcd_lane_settings(lt_settings,
252 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);