hwss/dcn35/dcn35_hwseq.c

100 		dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
101 		dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
103 	if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
105 		for (i = 0; i < dc->res_pool->stream_enc_count; i++)
106 			dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
108 		for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
109 			dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
132 	struct abm **abms = dc->res_pool->multiple_abms;
135 	struct resource_pool *res_pool = dc->res_pool;
182 	if (res_pool->dccg->funcs->dccg_init)
183 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
188 		res_pool->ref_clocks.xtalin_clock_inKhz =
191 		if (res_pool->dccg && res_pool->hubbub) {
193 			(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
195 				&res_pool->ref_clocks.dccg_ref_clock_inKhz);
197 			(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
198 				res_pool->ref_clocks.dccg_ref_clock_inKhz,
199 				&res_pool->ref_clocks.dchub_ref_clock_inKhz);
202 			res_pool->ref_clocks.dccg_ref_clock_inKhz =
203 				res_pool->ref_clocks.xtalin_clock_inKhz;
204 			res_pool->ref_clocks.dchub_ref_clock_inKhz =
205 				res_pool->ref_clocks.xtalin_clock_inKhz;
238 	if (res_pool->hubbub->funcs->dchubbub_init)
239 		res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);
250 			for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
251 				struct timing_generator *tg = dc->res_pool->timing_generators[i];
270 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
271 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
272 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
275 	for (i = 0; i < res_pool->audio_count; i++) {
276 		struct audio *audio = res_pool->audios[i];
290 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
328 	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
329 		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
339 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
340 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
341 				dc->res_pool->hubbub, false, false);
343 	if (dc->res_pool->hubbub->funcs->init_crb)
344 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
346 	if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
347 		dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
355 	if (dc->res_pool->pg_cntl) {
356 		if (dc->res_pool->pg_cntl->funcs->init_pg_status)
357 			dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);
492 	if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {
493 		hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
494 			hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
679 	struct hubbub *hubbub = dc->res_pool->hubbub;
680 	struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
690 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
691 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
717 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
719 		struct hubp *hubp = dc->res_pool->hubps[i];
732 	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
739 		dc->res_pool->mpc->funcs->mpc_init_single_inst(
740 				dc->res_pool->mpc, i);
743 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
744 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
745 		struct hubp *hubp = dc->res_pool->hubps[i];
746 		struct dpp *dpp = dc->res_pool->dpps[i];
781 		dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
782 		dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
783 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
784 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
811 			// We can't use res_pool->res_cap->num_timing_generator to check
816 			for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
818 				struct timing_generator *tg = dc->res_pool->timing_generators[i];
833 			for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
836 				dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);
842 				pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false);
889 	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
953 	for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {
955 				dc->res_pool->hpo_dp_stream_enc[i]) {
966 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
992 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
993 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
1019 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1080 	for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) {
1082 				dc->res_pool->hpo_dp_stream_enc[i]) {
1118 	struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
1130 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1137 	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)
1177 	struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
1188 	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)
1194 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1210 	struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
1216 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
1223 	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1226 				if (dc->res_pool->dccg->funcs->enable_dsc)
1227 					dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);
1229 				if (dc->res_pool->dccg->funcs->disable_dsc)
1230 					dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);
1236 		for (i = 0; i < dc->res_pool->pipe_count; i++) {